1 /*
2  * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32G4 processor
10  */
11 
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <stm32_ll_system.h>
15 #include <soc.h>
16 
17 #include <cmsis_core.h>
18 #if defined(PWR_CR3_UCPD_DBDIS)
19 #include <stm32_ll_bus.h>
20 #include <stm32_ll_pwr.h>
21 #endif /* PWR_CR3_UCPD_DBDIS */
22 
23 extern void stm32_power_init(void);
24 
25 /**
26  * @brief Perform basic hardware initialization at boot.
27  *
28  * This needs to be run from the very beginning.
29  */
soc_early_init_hook(void)30 void soc_early_init_hook(void)
31 {
32 	/* Enable ART Accelerator I/D-cache and prefetch */
33 	LL_FLASH_EnableInstCache();
34 	LL_FLASH_EnableDataCache();
35 	LL_FLASH_EnablePrefetch();
36 
37 	/* Update CMSIS SystemCoreClock variable (HCLK) */
38 	/* At reset, system core clock is set to 16 MHz from HSI */
39 	SystemCoreClock = 16000000;
40 
41 	/* allow reflashing board */
42 	LL_DBGMCU_EnableDBGSleepMode();
43 
44 #if defined(PWR_CR3_UCPD_DBDIS)
45 	if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) ||
46 		!IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) {
47 		/* Disable USB Type-C dead battery pull-down behavior */
48 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
49 		LL_PWR_DisableUCPDDeadBattery();
50 	}
51 
52 #endif /* PWR_CR3_UCPD_DBDIS */
53 #if CONFIG_PM
54 	stm32_power_init();
55 #endif
56 }
57