1 /* 2 * Copyright (c) 2024 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for Renesas RA6E2 family processor 10 */ 11 12 #include <zephyr/device.h> 13 #include <zephyr/init.h> 14 #include <zephyr/kernel.h> 15 #include <zephyr/arch/cpu.h> 16 #include <cmsis_core.h> 17 #include <zephyr/irq.h> 18 #include <zephyr/logging/log.h> 19 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); 20 21 #include "bsp_cfg.h" 22 #include <bsp_api.h> 23 24 uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; 25 26 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; 27 28 /** 29 * @brief Perform basic hardware initialization at boot. 30 * 31 * This needs to be run from the very beginning. 32 */ soc_early_init_hook(void)33void soc_early_init_hook(void) 34 { 35 uint32_t key; 36 37 key = irq_lock(); 38 39 extern volatile uint16_t g_protect_counters[]; 40 41 for (uint32_t i = 0; i < 4; i++) { 42 g_protect_counters[i] = 0; 43 } 44 45 #if FSP_PRIV_TZ_USE_SECURE_REGS 46 /* Disable protection using PRCR register. */ 47 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); 48 49 /* Initialize peripherals to secure mode for flat projects */ 50 R_PSCU->PSARB = 0; 51 R_PSCU->PSARC = 0; 52 R_PSCU->PSARD = 0; 53 R_PSCU->PSARE = 0; 54 55 R_CPSCU->ICUSARG = 0; 56 R_CPSCU->ICUSARH = 0; 57 R_CPSCU->ICUSARI = 0; 58 59 /* Enable protection using PRCR register. */ 60 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); 61 #endif 62 63 SystemCoreClock = BSP_MOCO_HZ; 64 g_protect_pfswe_counter = 0; 65 66 irq_unlock(key); 67 } 68
