1 /* 2 * Copyright (c) 2024 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for Renesas RA4M3 family processor 10 */ 11 12 #include <zephyr/device.h> 13 #include <zephyr/init.h> 14 #include <zephyr/kernel.h> 15 #include <zephyr/arch/cpu.h> 16 #include <cmsis_core.h> 17 #include <zephyr/arch/arm/nmi.h> 18 #include <zephyr/irq.h> 19 #include <zephyr/logging/log.h> 20 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); 21 22 #include "bsp_cfg.h" 23 #include <bsp_api.h> 24 25 uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; 26 27 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; 28 29 /** 30 * @brief Perform basic hardware initialization at boot. 31 * 32 * This needs to be run from the very beginning. 33 */ soc_early_init_hook(void)34void soc_early_init_hook(void) 35 { 36 extern volatile uint16_t g_protect_counters[]; 37 38 for (uint32_t i = 0; i < 4; i++) { 39 g_protect_counters[i] = 0; 40 } 41 42 #if FSP_PRIV_TZ_USE_SECURE_REGS 43 /* Disable protection using PRCR register. */ 44 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); 45 46 /* Initialize peripherals to secure mode for flat projects */ 47 R_PSCU->PSARB = 0; 48 R_PSCU->PSARC = 0; 49 R_PSCU->PSARD = 0; 50 R_PSCU->PSARE = 0; 51 52 R_CPSCU->ICUSARG = 0; 53 R_CPSCU->ICUSARH = 0; 54 R_CPSCU->ICUSARI = 0; 55 56 /* Enable protection using PRCR register. */ 57 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); 58 #endif 59 60 SystemCoreClock = BSP_MOCO_HZ; 61 g_protect_pfswe_counter = 0; 62 } 63
