1 /*
2  * Copyright 2022-2024 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _NXP_S32_S32ZE_SOC_H_
8 #define _NXP_S32_S32ZE_SOC_H_
9 
10 /* Do not let CMSIS to handle GIC */
11 #define __GIC_PRESENT 0
12 
13 #if defined(CONFIG_SOC_S32Z270)
14 #include <S32Z2.h>
15 #else
16 #error "SoC not supported"
17 #endif
18 
19 #if defined(CONFIG_CMSIS_RTOS_V2)
20 #include <cmsis_rtos_v2_adapt.h>
21 #endif
22 
23 /* Aliases for peripheral base addresses */
24 
25 /* LINFlexD*/
26 #define IP_LINFLEX_12_BASE      IP_MSC_0_LIN_BASE
27 
28 /* NETC */
29 #define IP_NETC_EMDIO_0_BASE    IP_NETC__EMDIO_BASE_BASE
30 
31 /* MRU */
32 #define IP_MRU_0_BASE           IP_RTU0__MRU_0_BASE
33 #define IP_MRU_1_BASE           IP_RTU0__MRU_1_BASE
34 #define IP_MRU_2_BASE           IP_RTU0__MRU_2_BASE
35 #define IP_MRU_3_BASE           IP_RTU0__MRU_3_BASE
36 #define IP_MRU_4_BASE           IP_RTU1__MRU_0_BASE
37 #define IP_MRU_5_BASE           IP_RTU1__MRU_1_BASE
38 #define IP_MRU_6_BASE           IP_RTU1__MRU_2_BASE
39 #define IP_MRU_7_BASE           IP_RTU1__MRU_3_BASE
40 
41 #endif /* _NXP_S32_S32ZE_SOC_H_ */
42