1 /*
2 * Copyright 2022,2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/device.h>
9 #include <zephyr/init.h>
10 #include <cmsis_core.h>
11 #include <zephyr/sys/barrier.h>
12 #include <zephyr/cache.h>
13
14 #include <OsIf.h>
15
soc_reset_hook(void)16 void soc_reset_hook(void)
17 {
18 /* enable peripheral port access at EL1 and EL0 */
19 __asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
20 __asm__ volatile("orr r0, #1\n");
21 __asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
22 barrier_dsync_fence_full();
23 barrier_isync_fence_full();
24
25 /*
26 * Take exceptions in Arm mode because Zephyr ASM code for Cortex-R Aarch32
27 * is written for Arm
28 */
29 __set_SCTLR(__get_SCTLR() & ~SCTLR_TE_Msk);
30
31 sys_cache_instr_enable();
32 sys_cache_data_enable();
33 }
34
soc_early_init_hook(void)35 void soc_early_init_hook(void)
36 {
37 OsIf_Init(NULL);
38 }
39
