1 /*
2  * Copyright 2022-2023 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #define SDRAM_BASE_ADDR 0x80000000
8 
9 #include <zephyr/devicetree.h>
10 #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
11 
12 static const struct arm_mpu_region mpu_regions[] = {
13 	/* Region 0 */
14 	MPU_REGION_ENTRY("FLASH_0",
15 			 CONFIG_FLASH_BASE_ADDRESS,
16 			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
17 	/* Region 1 */
18 	MPU_REGION_ENTRY("SRAM_0",
19 			 CONFIG_SRAM_BASE_ADDRESS,
20 			 REGION_RAM_ATTR(REGION_SRAM_SIZE)),
21 
22 #ifndef CONFIG_NXP_IMX_EXTERNAL_SDRAM
23 	/*
24 	 * Region 2 - mark SDRAM0 as device type memory to prevent core
25 	 * from executing speculative prefetches against this region when
26 	 * no SDRAM is present.
27 	 */
28 	MPU_REGION_ENTRY("SDRAM0", SDRAM_BASE_ADDR, REGION_IO_ATTR(REGION_512M)),
29 #endif
30 };
31 
32 const struct arm_mpu_config mpu_config = {
33 	.num_regions = ARRAY_SIZE(mpu_regions),
34 	.mpu_regions = mpu_regions,
35 };
36