1# Copyright 2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_SERIES_IMXRT10XX
5	select CPU_CORTEX_M7
6	select CPU_CORTEX_M_HAS_DWT
7	select CPU_HAS_ICACHE
8	select CPU_HAS_DCACHE
9	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
10	select ARM
11	select CLOCK_CONTROL
12	select HAS_MCUX
13	select HAS_MCUX_CACHE
14	select HAS_MCUX_12B1MSPS_SAR if !SOC_MIMXRT1042
15	select HAS_MCUX_CCM if !SOC_MIMXRT1042
16	select HAS_MCUX_FLEXSPI
17	select HAS_MCUX_IGPIO
18	select HAS_MCUX_LPI2C if !SOC_MIMXRT1042
19	select HAS_MCUX_LPSPI if !SOC_MIMXRT1042
20	select HAS_MCUX_LPUART if !SOC_MIMXRT1042
21	select HAS_MCUX_GPT if !SOC_MIMXRT1042
22	select HAS_MCUX_TRNG if !SOC_MIMXRT1042
23	select HAS_MCUX_EDMA
24	select HAS_MCUX_GPC
25	select HAS_MCUX_IOMUXC
26	select HAS_MCUX_PMU
27	select HAS_MCUX_DCDC
28	select HAS_MCUX_USB_EHCI
29	select HAS_SWO
30	select HAS_PM
31	select SOC_RESET_HOOK
32	select SOC_EARLY_INIT_HOOK
33
34config SOC_MIMXRT1011
35	select CPU_HAS_FPU
36	select CPU_HAS_ARM_MPU
37	select CPU_HAS_ICACHE
38	select CPU_HAS_DCACHE
39	select INIT_ENET_PLL
40
41config SOC_MIMXRT1015
42	select CPU_HAS_FPU
43	select CPU_HAS_FPU_DOUBLE_PRECISION
44	select CPU_HAS_ARM_MPU
45	select INIT_ENET_PLL
46
47config SOC_MIMXRT1021
48	select HAS_MCUX_ENET
49	select HAS_MCUX_SEMC
50	select CPU_HAS_FPU_DOUBLE_PRECISION
51	select CPU_HAS_ARM_MPU
52	select INIT_ENET_PLL
53	select HAS_MCUX_USDHC1
54	select HAS_MCUX_USDHC2
55	select HAS_MCUX_FLEXCAN
56	select HAS_MCUX_PWM
57
58config SOC_MIMXRT1024
59	select HAS_MCUX_ENET
60	select HAS_MCUX_SEMC
61	select CPU_HAS_FPU_DOUBLE_PRECISION
62	select CPU_HAS_ARM_MPU
63	select INIT_ENET_PLL
64	select HAS_MCUX_USDHC1
65	select HAS_MCUX_USDHC2
66	select HAS_MCUX_FLEXCAN
67	select HAS_MCUX_SRC
68
69config SOC_MIMXRT1042
70	select HAS_MCUX_SEMC
71	select CPU_HAS_FPU_DOUBLE_PRECISION
72	select CPU_HAS_ARM_MPU
73	select INIT_ARM_PLL
74	select INIT_SYS_PLL
75
76config SOC_MIMXRT1052
77	select HAS_MCUX_ELCDIF
78	select HAS_MCUX_ENET
79	select HAS_MCUX_SEMC
80	select CPU_HAS_FPU_DOUBLE_PRECISION
81	select CPU_HAS_ARM_MPU
82	select INIT_ARM_PLL
83	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
84	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
85	select HAS_MCUX_USDHC1
86	select HAS_MCUX_USDHC2
87	select HAS_MCUX_FLEXCAN
88	select HAS_MCUX_PWM
89	select HAS_MCUX_SRC
90	select HAS_MCUX_XBARA
91
92config SOC_MIMXRT1062
93	select HAS_MCUX_ELCDIF
94	select HAS_MCUX_ENET
95	select HAS_MCUX_PWM
96	select HAS_MCUX_QTMR
97	select HAS_MCUX_SEMC
98	select HAS_MCUX_SNVS
99	select CPU_HAS_FPU_DOUBLE_PRECISION
100	select CPU_HAS_ARM_MPU
101	select INIT_ARM_PLL
102	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
103	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
104	select HAS_MCUX_USDHC1
105	select HAS_MCUX_USDHC2
106	select HAS_MCUX_FLEXCAN
107	select HAS_MCUX_I2S
108	select HAS_MCUX_ADC_ETC
109	select HAS_MCUX_SRC
110	select HAS_MCUX_XBARA
111
112config SOC_MIMXRT1064
113	select HAS_MCUX_ELCDIF
114	select HAS_MCUX_ENET
115	select HAS_MCUX_PWM
116	select HAS_MCUX_QTMR
117	select HAS_MCUX_SEMC
118	select HAS_MCUX_SNVS
119	select HAS_MCUX_SRC
120	select CPU_HAS_FPU_DOUBLE_PRECISION
121	select CPU_HAS_ARM_MPU
122	select INIT_ARM_PLL
123	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
124	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
125	select HAS_MCUX_USDHC1
126	select HAS_MCUX_USDHC2
127	select HAS_MCUX_FLEXCAN
128	select HAS_SWO
129