1# MIMX8ML8 SoC defconfig
2
3# Copyright (c) 2021, Laird Connectivity
4# Copyright 2024 NXP
5# SPDX-License-Identifier: Apache-2.0
6
7if SOC_MIMX8ML8_M7
8
9config SYS_CLOCK_HW_CYCLES_PER_SEC
10	default 800000000
11
12config GPIO
13	default y
14
15config IPM_IMX
16	default y
17	depends on IPM
18
19if CODE_ITCM
20
21config FLASH_SIZE
22	default $(dt_node_reg_size_int,/soc/itcm@0,0,K)
23
24config FLASH_BASE_ADDRESS
25	default $(dt_node_reg_addr_hex,/soc/itcm@0)
26
27endif # CODE_ITCM
28
29if CODE_DDR
30
31config FLASH_SIZE
32	default $(dt_node_reg_size_int,/soc/code@80000000,0,K)
33
34config FLASH_BASE_ADDRESS
35	default $(dt_node_reg_addr_hex,/soc/code@80000000)
36
37endif # CODE_DDR
38
39config NUM_IRQS
40	# must be >= the highest interrupt number used
41	default 159
42
43endif # SOC_MIMX8ML8_M7
44