1 /*
2 * Copyright (c) 2021, Antonio Tessarolo
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <ccm_imx6sx.h>
8 #include <ccm_analog_imx6sx.h>
9 #include "soc_clk_freq.h"
10
11 #ifdef CONFIG_PWM_IMX
12
get_pwm_clock_freq(PWM_Type * base)13 uint32_t get_pwm_clock_freq(PWM_Type *base)
14 {
15 uint32_t root;
16 uint32_t hz;
17 uint32_t divPerclkPodf, divIpgPodf, divAhbPodf, divPeriphClk2Podf;
18
19 /* Different instance has the same clock root, it's different from i.mx7d. */
20 /* Get the clock root according to the mux node of clock tree. */
21 if (CCM_GetRootMux(CCM, ccmRootPerclkClkSel) ==
22 ccmRootmuxPerclkClkOsc24m) {
23 root = ccmRootmuxPerclkClkOsc24m;
24 hz = 24000000;
25 divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
26 divIpgPodf = 0;
27 divAhbPodf = 0;
28 divPeriphClk2Podf = 0;
29 } else if (CCM_GetRootMux(CCM, ccmRootPeriphClkSel) ==
30 ccmRootmuxPeriphClkPrePeriphClkSel) {
31 root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel);
32 /* Here do not show all the clock root source,
33 * if user use other clock root source, such as PLL2_PFD2, please
34 * add it as follows according to the clock tree of CCM in reference manual.
35 */
36 switch (root) {
37 case ccmRootmuxPrePeriphClkPll2:
38 hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllSysControl);
39 divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
40 divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
41 divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
42 divPeriphClk2Podf = 0;
43 break;
44 default:
45 return 0;
46 }
47 } else if (CCM_GetRootMux(CCM, ccmRootPeriphClk2Sel) ==
48 ccmRootmuxPeriphClk2OSC24m) {
49 root = ccmRootmuxPeriphClk2OSC24m;
50 hz = 24000000;
51 divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
52 divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
53 divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
54 divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
55 } else {
56 root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel);
57 /* Here do not show all the clock root source,
58 * if user use other clock root source, such as PLL3_BYP, please
59 * add it as follows according to the clock tree of CCM in reference manual.
60 */
61 switch (root) {
62 case ccmRootmuxPll3SwClkPll3:
63 hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control);
64 divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
65 divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
66 divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
67 divPeriphClk2Podf =
68 CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
69 break;
70 default:
71 return 0;
72 }
73 }
74
75 return hz / (divPerclkPodf + 1) / (divIpgPodf + 1) /
76 (divAhbPodf + 1) / (divPeriphClk2Podf + 1);
77 }
78
79 #endif /* CONFIG_PWM_IMX */
80
