1 /* 2 * Copyright (c) 2019, 2020 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/kernel.h> 8 #include <zephyr/devicetree.h> 9 10 #include <nrfx.h> 11 12 /* 13 * Account for MDK inconsistencies 14 */ 15 16 #if !defined(NRF_CTRLAP) && defined(NRF_CTRL_AP_PERI) 17 #define NRF_CTRLAP NRF_CTRL_AP_PERI 18 #endif 19 20 #if !defined(NRF_GPIOTE0) && defined(NRF_GPIOTE) 21 #define NRF_GPIOTE0 NRF_GPIOTE 22 #endif 23 24 #if !defined(NRF_I2S0) && defined(NRF_I2S) 25 #define NRF_I2S0 NRF_I2S 26 #endif 27 28 #if !defined(NRF_P0) && defined(NRF_GPIO) 29 #define NRF_P0 NRF_GPIO 30 #endif 31 32 #if !defined(NRF_PDM0) && defined(NRF_PDM) 33 #define NRF_PDM0 NRF_PDM 34 #endif 35 36 #if !defined(NRF_QDEC0) && defined(NRF_QDEC) 37 #define NRF_QDEC0 NRF_QDEC 38 #endif 39 40 #if !defined(NRF_RADIO) && defined(NRF_RADIOCORE_RADIO) 41 #define NRF_RADIO NRF_RADIOCORE_RADIO 42 #endif 43 44 #if !defined(NRF_RTC) && defined(NRF_RADIOCORE_RTC) 45 #define NRF_RTC NRF_RADIOCORE_RTC 46 #endif 47 48 #if !defined(NRF_SWI0) && defined(NRF_SWI_BASE) 49 #define NRF_SWI0 ((0 * 0x1000) + NRF_SWI_BASE) 50 #endif 51 52 #if !defined(NRF_SWI1) && defined(NRF_SWI_BASE) 53 #define NRF_SWI1 ((1 * 0x1000) + NRF_SWI_BASE) 54 #endif 55 56 #if !defined(NRF_SWI2) && defined(NRF_SWI_BASE) 57 #define NRF_SWI2 ((2 * 0x1000) + NRF_SWI_BASE) 58 #endif 59 60 #if !defined(NRF_SWI3) && defined(NRF_SWI_BASE) 61 #define NRF_SWI3 ((3 * 0x1000) + NRF_SWI_BASE) 62 #endif 63 64 #if !defined(NRF_SWI4) && defined(NRF_SWI_BASE) 65 #define NRF_SWI4 ((4 * 0x1000) + NRF_SWI_BASE) 66 #endif 67 68 #if !defined(NRF_SWI5) && defined(NRF_SWI_BASE) 69 #define NRF_SWI5 ((5 * 0x1000) + NRF_SWI_BASE) 70 #endif 71 72 #if !defined(NRF_WDT0) && defined(NRF_WDT) 73 #define NRF_WDT0 NRF_WDT 74 #endif 75 76 #if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X) 77 #if !defined(NRF_POWER_GPREGRET1) && defined(NRF_POWER_BASE) 78 #define NRF_POWER_GPREGRET1 (0x51c + NRF_POWER_BASE) 79 #endif 80 81 #if !defined(NRF_POWER_GPREGRET2) && defined(NRF_POWER_BASE) 82 #define NRF_POWER_GPREGRET2 (0x520 + NRF_POWER_BASE) 83 #endif 84 #endif 85 86 /** 87 * Check that a devicetree node's "reg" base address matches the 88 * correct value from the MDK. 89 * 90 * Node reg values are checked against MDK addresses regardless of 91 * their status. 92 * 93 * Using a node label allows the same file to work with multiple SoCs 94 * and devicetree configurations. 95 * 96 * @param lbl lowercase-and-underscores devicetree node label to check 97 * @param mdk_addr expected address from the Nordic MDK. 98 */ 99 #define CHECK_DT_REG(lbl, mdk_addr) \ 100 BUILD_ASSERT( \ 101 UTIL_OR(UTIL_NOT(DT_REG_HAS_IDX(DT_NODELABEL(lbl), 0)), \ 102 (DT_REG_ADDR(DT_NODELABEL(lbl)) == (uint32_t)(mdk_addr)))) 103 104 /** 105 * If a node label "lbl" might have different addresses depending on 106 * its compatible "compat", you can use this macro to pick the right 107 * one. 108 * 109 * @param lbl lowercase-and-underscores devicetree node label to check 110 * @param compat lowercase-and-underscores compatible to check 111 * @param addr_if_match MDK address to return if "lbl" has compatible "compat" 112 * @param addr_if_no_match MDK address to return otherwise 113 */ 114 #define NODE_ADDRESS(lbl, compat, addr_if_match, addr_if_no_match) \ 115 COND_CODE_1(DT_NODE_HAS_COMPAT(DT_NODELABEL(lbl), compat), \ 116 (addr_if_match), (addr_if_no_match)) 117 118 #define CHECK_SPI_REG(lbl, num) \ 119 CHECK_DT_REG(lbl, \ 120 NODE_ADDRESS(lbl, nordic_nrf_spi, NRF_SPI##num, \ 121 NODE_ADDRESS(lbl, nordic_nrf_spim, NRF_SPIM##num, \ 122 NRF_SPIS##num))) 123 124 #define CHECK_I2C_REG(lbl, num) \ 125 CHECK_DT_REG(lbl, \ 126 NODE_ADDRESS(lbl, nordic_nrf_twi, NRF_TWI##num, \ 127 NODE_ADDRESS(lbl, nordic_nrf_twim, NRF_TWIM##num, \ 128 NRF_TWIS##num))) 129 130 #define CHECK_UART_REG(lbl, num) \ 131 CHECK_DT_REG(lbl, \ 132 NODE_ADDRESS(lbl, nordic_nrf_uart, NRF_UART##num, \ 133 NRF_UARTE##num)) 134 135 CHECK_DT_REG(acl, NRF_ACL); 136 CHECK_DT_REG(adc, NODE_ADDRESS(adc, nordic_nrf_adc, NRF_ADC, NRF_SAADC)); 137 CHECK_DT_REG(cpusec_bellboard, NRF_SECDOMBELLBOARD); 138 CHECK_DT_REG(cpuapp_bellboard, NRF_APPLICATION_BELLBOARD); 139 CHECK_DT_REG(cpurad_bellboard, NRF_RADIOCORE_BELLBOARD); 140 CHECK_DT_REG(bprot, NRF_BPROT); 141 CHECK_DT_REG(ccm, NRF_CCM); 142 CHECK_DT_REG(ccm030, NRF_RADIOCORE_CCM030); 143 CHECK_DT_REG(ccm031, NRF_RADIOCORE_CCM031); 144 CHECK_DT_REG(clock, NRF_CLOCK); 145 CHECK_DT_REG(comp, NODE_ADDRESS(comp, nordic_nrf_comp, NRF_COMP, NRF_LPCOMP)); 146 CHECK_DT_REG(cryptocell, NRF_CRYPTOCELL); 147 CHECK_DT_REG(ctrlap, NRF_CTRLAP); 148 CHECK_DT_REG(dcnf, NRF_DCNF); 149 CHECK_DT_REG(dppic, NRF_DPPIC); 150 CHECK_DT_REG(dppic00, NRF_DPPIC00); 151 CHECK_DT_REG(dppic10, NRF_DPPIC10); 152 CHECK_DT_REG(dppic20, NRF_DPPIC20); 153 CHECK_DT_REG(dppic30, NRF_DPPIC30); 154 CHECK_DT_REG(dppic020, NRF_RADIOCORE_DPPIC020); 155 CHECK_DT_REG(dppic120, NRF_DPPIC120); 156 CHECK_DT_REG(dppic130, NRF_DPPIC130); 157 CHECK_DT_REG(dppic131, NRF_DPPIC131); 158 CHECK_DT_REG(dppic132, NRF_DPPIC132); 159 CHECK_DT_REG(dppic133, NRF_DPPIC133); 160 CHECK_DT_REG(dppic134, NRF_DPPIC134); 161 CHECK_DT_REG(dppic135, NRF_DPPIC135); 162 CHECK_DT_REG(dppic136, NRF_DPPIC136); 163 CHECK_DT_REG(ecb, NRF_ECB); 164 CHECK_DT_REG(ecb020, NRF_ECB020); 165 CHECK_DT_REG(ecb030, NRF_RADIOCORE_ECB030); 166 CHECK_DT_REG(ecb031, NRF_RADIOCORE_ECB031); 167 CHECK_DT_REG(egu0, NRF_EGU0); 168 CHECK_DT_REG(egu1, NRF_EGU1); 169 CHECK_DT_REG(egu2, NRF_EGU2); 170 CHECK_DT_REG(egu3, NRF_EGU3); 171 CHECK_DT_REG(egu4, NRF_EGU4); 172 CHECK_DT_REG(egu5, NRF_EGU5); 173 CHECK_DT_REG(egu10, NRF_EGU10); 174 CHECK_DT_REG(egu20, NRF_EGU20); 175 CHECK_DT_REG(egu020, NRF_RADIOCORE_EGU020); 176 CHECK_DT_REG(egu130, NRF_EGU130); 177 CHECK_DT_REG(ficr, NRF_FICR); 178 CHECK_DT_REG(flash_controller, NRF_NVMC); 179 CHECK_DT_REG(gpio0, NRF_P0); 180 CHECK_DT_REG(gpio1, NRF_P1); 181 CHECK_DT_REG(gpio2, NRF_P2); 182 CHECK_DT_REG(gpio6, NRF_P6); 183 CHECK_DT_REG(gpio7, NRF_P7); 184 CHECK_DT_REG(gpio9, NRF_P9); 185 CHECK_DT_REG(gpiote, NRF_GPIOTE); 186 CHECK_DT_REG(gpiote0, NRF_GPIOTE0); 187 CHECK_DT_REG(gpiote1, NRF_GPIOTE1); 188 CHECK_DT_REG(gpiote20, NRF_GPIOTE20); 189 CHECK_DT_REG(gpiote30, NRF_GPIOTE30); 190 CHECK_DT_REG(gpiote130, NRF_GPIOTE130); 191 CHECK_DT_REG(gpiote131, NRF_GPIOTE131); 192 CHECK_DT_REG(grtc, NRF_GRTC); 193 CHECK_DT_REG(cpuapp_hsfll, NRF_APPLICATION_HSFLL); 194 CHECK_DT_REG(cpurad_hsfll, NRF_RADIOCORE_HSFLL); 195 CHECK_I2C_REG(i2c0, 0); 196 CHECK_I2C_REG(i2c1, 1); 197 CHECK_DT_REG(i2c2, NRF_TWIM2); 198 CHECK_DT_REG(i2c3, NRF_TWIM3); 199 CHECK_DT_REG(i2c20, NRF_TWIM20); 200 CHECK_DT_REG(i2c21, NRF_TWIM21); 201 CHECK_DT_REG(i2c22, NRF_TWIM22); 202 CHECK_DT_REG(i2c30, NRF_TWIM30); 203 CHECK_DT_REG(i2c130, NRF_TWIM130); 204 CHECK_DT_REG(i2c131, NRF_TWIM131); 205 CHECK_DT_REG(i2c132, NRF_TWIM132); 206 CHECK_DT_REG(i2c133, NRF_TWIM133); 207 CHECK_DT_REG(i2c134, NRF_TWIM134); 208 CHECK_DT_REG(i2c135, NRF_TWIM135); 209 CHECK_DT_REG(i2c136, NRF_TWIM136); 210 CHECK_DT_REG(i2c137, NRF_TWIM137); 211 CHECK_DT_REG(i2s0, NRF_I2S0); 212 CHECK_DT_REG(i2s20, NRF_I2S20); 213 CHECK_DT_REG(ipc, NRF_IPC); 214 CHECK_DT_REG(cpuapp_ipct, NRF_APPLICATION_IPCT); 215 CHECK_DT_REG(cpurad_ipct, NRF_RADIOCORE_IPCT); 216 CHECK_DT_REG(ipct120, NRF_IPCT120); 217 CHECK_DT_REG(ipct130, NRF_IPCT130); 218 CHECK_DT_REG(kmu, NRF_KMU); 219 CHECK_DT_REG(mutex, NRF_MUTEX); 220 CHECK_DT_REG(mwu, NRF_MWU); 221 CHECK_DT_REG(nfct, NRF_NFCT); 222 CHECK_DT_REG(nrf_mpu, NRF_MPU); 223 CHECK_DT_REG(oscillators, NRF_OSCILLATORS); 224 CHECK_DT_REG(pdm0, NRF_PDM0); 225 CHECK_DT_REG(pdm20, NRF_PDM20); 226 CHECK_DT_REG(pdm21, NRF_PDM21); 227 CHECK_DT_REG(power, NRF_POWER); 228 CHECK_DT_REG(ppi, NRF_PPI); 229 CHECK_DT_REG(pwm0, NRF_PWM0); 230 CHECK_DT_REG(pwm1, NRF_PWM1); 231 CHECK_DT_REG(pwm2, NRF_PWM2); 232 CHECK_DT_REG(pwm3, NRF_PWM3); 233 CHECK_DT_REG(pwm20, NRF_PWM20); 234 CHECK_DT_REG(pwm21, NRF_PWM21); 235 CHECK_DT_REG(pwm22, NRF_PWM22); 236 CHECK_DT_REG(pwm120, NRF_PWM120); 237 CHECK_DT_REG(pwm130, NRF_PWM130); 238 CHECK_DT_REG(pwm131, NRF_PWM131); 239 CHECK_DT_REG(pwm132, NRF_PWM132); 240 CHECK_DT_REG(pwm133, NRF_PWM133); 241 CHECK_DT_REG(qdec, NRF_QDEC0); /* this should be the same node as qdec0 */ 242 CHECK_DT_REG(qdec0, NRF_QDEC0); 243 CHECK_DT_REG(qdec1, NRF_QDEC1); 244 CHECK_DT_REG(qdec20, NRF_QDEC20); 245 CHECK_DT_REG(qdec21, NRF_QDEC21); 246 CHECK_DT_REG(qdec130, NRF_QDEC130); 247 CHECK_DT_REG(qdec131, NRF_QDEC131); 248 CHECK_DT_REG(radio, NRF_RADIO); 249 CHECK_DT_REG(regulators, NRF_REGULATORS); 250 CHECK_DT_REG(reset, NRF_RESET); 251 CHECK_DT_REG(cpuapp_resetinfo, NRF_APPLICATION_RESETINFO); 252 CHECK_DT_REG(cpurad_resetinfo, NRF_RADIOCORE_RESETINFO); 253 CHECK_DT_REG(rng, NRF_RNG); 254 CHECK_DT_REG(rtc, NRF_RTC); 255 CHECK_DT_REG(rtc0, NRF_RTC0); 256 CHECK_DT_REG(rtc1, NRF_RTC1); 257 CHECK_DT_REG(rtc2, NRF_RTC2); 258 CHECK_DT_REG(rtc130, NRF_RTC130); 259 CHECK_DT_REG(rtc131, NRF_RTC131); 260 CHECK_SPI_REG(spi0, 0); 261 CHECK_SPI_REG(spi1, 1); 262 CHECK_SPI_REG(spi2, 2); 263 CHECK_DT_REG(spi3, NRF_SPIM3); 264 CHECK_DT_REG(spi4, NRF_SPIM4); 265 CHECK_DT_REG(spi00, NRF_SPIM00); 266 CHECK_DT_REG(spi20, NRF_SPIM20); 267 CHECK_DT_REG(spi21, NRF_SPIM21); 268 CHECK_DT_REG(spi22, NRF_SPIM22); 269 CHECK_DT_REG(spi30, NRF_SPIM30); 270 CHECK_DT_REG(spi120, NRF_SPIM120); 271 CHECK_DT_REG(spi121, NRF_SPIM121); 272 CHECK_DT_REG(spi130, NRF_SPIM130); 273 CHECK_DT_REG(spi131, NRF_SPIM131); 274 CHECK_DT_REG(spi132, NRF_SPIM132); 275 CHECK_DT_REG(spi133, NRF_SPIM133); 276 CHECK_DT_REG(spi134, NRF_SPIM134); 277 CHECK_DT_REG(spi135, NRF_SPIM135); 278 CHECK_DT_REG(spi136, NRF_SPIM136); 279 CHECK_DT_REG(spi137, NRF_SPIM137); 280 CHECK_DT_REG(spu, NRF_SPU); 281 CHECK_DT_REG(swi0, NRF_SWI0); 282 CHECK_DT_REG(swi1, NRF_SWI1); 283 CHECK_DT_REG(swi2, NRF_SWI2); 284 CHECK_DT_REG(swi3, NRF_SWI3); 285 CHECK_DT_REG(swi4, NRF_SWI4); 286 CHECK_DT_REG(swi5, NRF_SWI5); 287 CHECK_DT_REG(temp, NRF_TEMP); 288 CHECK_DT_REG(timer0, NRF_TIMER0); 289 CHECK_DT_REG(timer1, NRF_TIMER1); 290 CHECK_DT_REG(timer2, NRF_TIMER2); 291 CHECK_DT_REG(timer3, NRF_TIMER3); 292 CHECK_DT_REG(timer4, NRF_TIMER4); 293 CHECK_DT_REG(timer00, NRF_TIMER00); 294 CHECK_DT_REG(timer10, NRF_TIMER10); 295 CHECK_DT_REG(timer20, NRF_TIMER20); 296 CHECK_DT_REG(timer21, NRF_TIMER21); 297 CHECK_DT_REG(timer22, NRF_TIMER22); 298 CHECK_DT_REG(timer23, NRF_TIMER23); 299 CHECK_DT_REG(timer24, NRF_TIMER24); 300 CHECK_DT_REG(timer020, NRF_RADIOCORE_TIMER020); 301 CHECK_DT_REG(timer021, NRF_RADIOCORE_TIMER021); 302 CHECK_DT_REG(timer022, NRF_RADIOCORE_TIMER022); 303 CHECK_DT_REG(timer120, NRF_TIMER120); 304 CHECK_DT_REG(timer121, NRF_TIMER121); 305 CHECK_DT_REG(timer130, NRF_TIMER130); 306 CHECK_DT_REG(timer131, NRF_TIMER131); 307 CHECK_DT_REG(timer132, NRF_TIMER132); 308 CHECK_DT_REG(timer133, NRF_TIMER133); 309 CHECK_DT_REG(timer134, NRF_TIMER134); 310 CHECK_DT_REG(timer135, NRF_TIMER135); 311 CHECK_DT_REG(timer136, NRF_TIMER136); 312 CHECK_DT_REG(timer137, NRF_TIMER137); 313 CHECK_UART_REG(uart0, 0); 314 CHECK_DT_REG(uart1, NRF_UARTE1); 315 CHECK_DT_REG(uart2, NRF_UARTE2); 316 CHECK_DT_REG(uart3, NRF_UARTE3); 317 CHECK_DT_REG(uart00, NRF_UARTE00); 318 CHECK_DT_REG(uart20, NRF_UARTE20); 319 CHECK_DT_REG(uart21, NRF_UARTE21); 320 CHECK_DT_REG(uart22, NRF_UARTE22); 321 CHECK_DT_REG(uart30, NRF_UARTE30); 322 CHECK_DT_REG(uart120, NRF_UARTE120); 323 CHECK_DT_REG(uart130, NRF_UARTE130); 324 CHECK_DT_REG(uart131, NRF_UARTE131); 325 CHECK_DT_REG(uart132, NRF_UARTE132); 326 CHECK_DT_REG(uart133, NRF_UARTE133); 327 CHECK_DT_REG(uart134, NRF_UARTE134); 328 CHECK_DT_REG(uart135, NRF_UARTE135); 329 CHECK_DT_REG(uart136, NRF_UARTE136); 330 CHECK_DT_REG(uart137, NRF_UARTE137); 331 CHECK_DT_REG(uicr, NRF_UICR); 332 CHECK_DT_REG(cpuapp_uicr, NRF_APPLICATION_UICR); 333 CHECK_DT_REG(bicr, NRF_APPLICATION_BICR); 334 CHECK_DT_REG(cpurad_uicr, NRF_RADIOCORE_UICR); 335 CHECK_DT_REG(usbd, NRF_USBD); 336 CHECK_DT_REG(usbhs, NRF_USBHS); 337 CHECK_DT_REG(usbhs_core, NRF_USBHSCORE0); 338 CHECK_DT_REG(usbreg, NRF_USBREGULATOR); 339 CHECK_DT_REG(vmc, NRF_VMC); 340 CHECK_DT_REG(cpuflpr_clic, NRF_FLPR_VPRCLIC); 341 CHECK_DT_REG(cpuppr_clic, NRF_PPR_VPRCLIC); 342 #if defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15) 343 CHECK_DT_REG(cpuflpr_vpr, NRF_VPR00); 344 #elif defined(CONFIG_NRF_PLATFORM_HALTIUM) 345 CHECK_DT_REG(cpuflpr_vpr, NRF_VPR121); 346 CHECK_DT_REG(cpuppr_vpr, NRF_VPR130); 347 #endif 348 CHECK_DT_REG(wdt, NRF_WDT0); /* this should be the same node as wdt0 */ 349 CHECK_DT_REG(wdt0, NRF_WDT0); 350 CHECK_DT_REG(wdt1, NRF_WDT1); 351 CHECK_DT_REG(wdt30, NRF_WDT30); 352 CHECK_DT_REG(wdt31, NRF_WDT31); 353 CHECK_DT_REG(cpuapp_wdt010, NRF_APPLICATION_WDT010); 354 CHECK_DT_REG(cpuapp_wdt011, NRF_APPLICATION_WDT011); 355 CHECK_DT_REG(cpurad_wdt010, NRF_RADIOCORE_WDT010); 356 CHECK_DT_REG(cpurad_wdt011, NRF_RADIOCORE_WDT011); 357 CHECK_DT_REG(wdt131, NRF_WDT131); 358 CHECK_DT_REG(wdt132, NRF_WDT132); 359 360 /* nRF51/nRF52-specific addresses */ 361 #if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X) 362 CHECK_DT_REG(gpregret1, NRF_POWER_GPREGRET1); 363 CHECK_DT_REG(gpregret2, NRF_POWER_GPREGRET2); 364 #endif 365
