1# RISCV64_MIV Microchip Polarfire SOC configuration options 2 3# Copyright (c) 2020-2021 Microchip Technology Inc 4# SPDX-License-Identifier: Apache-2.0 5 6config SOC_SERIES_POLARFIRE 7 select RISCV 8 select RISCV_PRIVILEGED 9 select RISCV_HAS_PLIC 10 select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING 11 imply XIP 12 13config SOC_POLARFIRE 14 select 64BIT 15 select SCHED_IPI_SUPPORTED 16 select ATOMIC_OPERATIONS_BUILTIN 17 select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING 18 select USE_SWITCH_SUPPORTED 19 select USE_SWITCH 20 21config SOC_POLARFIRE_U54 22 select CPU_HAS_FPU 23 select CPU_HAS_FPU_DOUBLE_PRECISION 24 select RISCV_ISA_RV64I 25 select RISCV_ISA_EXT_G 26 select RISCV_ISA_EXT_C 27 28config SOC_POLARFIRE_E51 29 select RISCV_ISA_RV64I 30 select RISCV_ISA_EXT_M 31 select RISCV_ISA_EXT_A 32 select RISCV_ISA_EXT_C 33 select RISCV_ISA_EXT_ZICSR 34 select RISCV_ISA_EXT_ZIFENCEI 35 36config MPFS_HAL 37 depends on SOC_POLARFIRE 38 bool "Microchip Polarfire SOC hardware abstracton layer" 39 select HAS_MPFS_HAL 40
