1 /*
2  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _MEC172X_EMI_H
8 #define _MEC172X_EMI_H
9 
10 #include <stdint.h>
11 #include <stddef.h>
12 
13 /** @brief Embedded Memory Interface (EMI) Registers */
14 struct emi_regs {
15 	volatile uint8_t RT_HOST_TO_EC;
16 	volatile uint8_t RT_EC_TO_HOST;
17 	volatile uint8_t EC_ADDR_LSB;
18 	volatile uint8_t EC_ADDR_MSB;
19 	volatile uint8_t EC_DATA_0;		/* +0x04 */
20 	volatile uint8_t EC_DATA_1;
21 	volatile uint8_t EC_DATA_2;
22 	volatile uint8_t EC_DATA_3;
23 	volatile uint8_t INTR_SRC_LSB;	/* +0x08 */
24 	volatile uint8_t INTR_SRC_MSB;
25 	volatile uint8_t INTR_MSK_LSB;
26 	volatile uint8_t INTR_MSK_MSB;
27 	volatile uint8_t APPID;			/* +0x0C */
28 	uint8_t RSVD1[3];
29 	volatile uint8_t APPID_ASSGN;	/* +0x10 */
30 	uint8_t RSVD2[3];
31 	uint32_t RSVD3[(0x100 - 0x14) / 4];
32 	volatile uint8_t HOST_TO_EC;	/* +0x100 */
33 	volatile uint8_t EC_TO_HOST;
34 	uint16_t RSVD4[1];
35 	volatile uint32_t MEM_BA_0;		/* +0x104 */
36 	volatile uint16_t MEM_RL_0;		/* +0x108 */
37 	volatile uint16_t MEM_WL_0;
38 	volatile uint32_t MEM_BA_1;		/* +0x10C */
39 	volatile uint16_t MEM_RL_1;		/* +0x110 */
40 	volatile uint16_t MEM_WL_1;
41 	volatile uint16_t INTR_SET;		/* +0x114 */
42 	volatile uint16_t HOST_CLR_EN;	/* +0x116 */
43 	uint32_t RSVD5[2];
44 	volatile uint32_t APPID_STS_1;	/* +0x120 */
45 	volatile uint32_t APPID_STS_2;
46 	volatile uint32_t APPID_STS_3;
47 	volatile uint32_t APPID_STS_4;
48 };
49 
50 #endif /* #ifndef _MEC172X_EMI_H */
51