1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_ACPI_EC_H 8 #define _MEC_ACPI_EC_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define MCHP_ACPI_EC_SPACING 0x0400u 14 #define MCHP_ACPI_EC_SPACING_PWROF2 10 15 16 /* EC_STS and OS_CMD_STS(read) bit definitions */ 17 #define MCHP_ACPI_EC_STS_OBF_POS 0 18 #define MCHP_ACPI_EC_STS_OBF BIT(MCHP_ACPI_EC_STS_OBF_POS) 19 #define MCHP_ACPI_EC_STS_IBF_POS 1 20 #define MCHP_ACPI_EC_STS_IBF BIT(MCHP_ACPI_EC_STS_IBF_POS) 21 #define MCHP_ACPI_EC_STS_UD1A_POS 2 22 #define MCHP_ACPI_EC_STS_UD1A BIT(MCHP_ACPI_EC_STS_UD1A_POS) 23 #define MCHP_ACPI_EC_STS_CMD_POS 3 24 #define MCHP_ACPI_EC_STS_CMD BIT(MCHP_ACPI_EC_STS_CMD_POS) 25 #define MCHP_ACPI_EC_STS_BURST_POS 4 26 #define MCHP_ACPI_EC_STS_BURST BIT(MCHP_ACPI_EC_STS_BURST_POS) 27 #define MCHP_ACPI_EC_STS_SCI_POS 5 28 #define MCHP_ACPI_EC_STS_SCI BIT(MCHP_ACPI_EC_STS_SCI_POS) 29 #define MCHP_ACPI_EC_STS_SMI_POS 6 30 #define MCHP_ACPI_EC_STS_SMI BIT(MCHP_ACPI_EC_STS_SMI_POS) 31 #define MCHP_ACPI_EC_STS_UD0A_POS 7 32 #define MCHP_ACPI_EC_STS_UD0A BIT(MCHP_ACPI_EC_STS_UD0A_POS) 33 34 /* EC_BYTE_CTRL and OS_BYTE_CTRL */ 35 #define MCHP_ACPI_EC_BYTE_CTRL_4B_POS 0 36 #define MCHP_ACPI_EC_BYTE_CTRL_4B_EN BIT(MCHP_ACPI_EC_BYTE_CTRL_4B_POS) 37 38 /* ACPI_PM1 peripheral */ 39 40 /* ACPI_PM1 RT/EC Status 1 */ 41 #define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0 42 #define MCHP_ACPI_PM1_EC_STS1_REG_OFS 0x0100u 43 #define MCHP_ACPI_PM1_STS1_REG_MASK 0x0000u 44 45 /* ACPI_PM1 RT/EC Status 2 */ 46 #define MCHP_ACPI_PM1_RT_STS2_REG_OFS 1u 47 #define MCHP_ACPI_PM1_EC_STS2_REG_OFS 0x0101u 48 #define MCHP_ACPI_PM1_STS2_REG_MASK 0x008fu 49 #define MCHP_ACPI_PM1_STS2_PWRBTN BIT(0) 50 #define MCHP_ACPI_PM1_STS2_SLPBTN BIT(1) 51 #define MCHP_ACPI_PM1_STS2_RTC BIT(2) 52 #define MCHP_ACPI_PM1_STS2_PWRBTNOR BIT(3) 53 #define MCHP_ACPI_PM1_STS2_WAK BIT(7) 54 55 /* ACPI_PM1 RT/EC Enable 1 */ 56 #define MCHP_ACPI_PM1_RT_EN1_REG_OFS 0x0002u 57 #define MCHP_ACPI_PM1_EC_EN1_REG_OFS 0x0102u 58 #define MCHP_ACPI_PM1_EN1_REG_MASK 0u 59 60 /* ACPI_PM1 RT/EC Enable 2 */ 61 #define MCHP_ACPI_PM1_RT_EN2_REG_OFS 3u 62 #define MCHP_ACPI_PM1_EC_EN2_REG_OFS 0x0103u 63 #define MCHP_ACPI_PM1_EN2_REG_MASK 0x0007u 64 #define MCHP_ACPI_PM1_EN2_PWRBTN BIT(0) 65 #define MCHP_ACPI_PM1_EN2_SLPBTN BIT(1) 66 #define MCHP_ACPI_PM1_EN2_RTC BIT(2) 67 68 /* ACPI_PM1 RT/EC Control 1 */ 69 #define MCHP_ACPI_PM1_RT_CTRL1_REG_OFS 4u 70 #define MCHP_ACPI_PM1_EC_CTRL1_REG_OFS 0x0104u 71 #define MCHP_ACPI_PM1_CTRL1_REG_MASK 0u 72 73 /* ACPI_PM1 RT/EC Control 2 */ 74 #define MCHP_ACPI_PM1_RT_CTRL2_REG_OFS 5ul 75 #define MCHP_ACPI_PM1_EC_CTRL2_REG_OFS 0x0105u 76 #define MCHP_ACPI_PM1_CTRL2_REG_MASK 0x003eu 77 #define MCHP_ACPI_PM1_CTRL2_PWRBTNOR_EN BIT(1) 78 #define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_POS 2 79 #define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK SHLU32(3, 2) 80 #define MCHP_ACPI_PM1_CTRL2_SLP_EN BIT(5) 81 82 /* ACPI_PM1 RT/EC Control 21 */ 83 #define MCHP_ACPI_PM1_RT_CTRL21_REG_OFS 0x0006u 84 #define MCHP_ACPI_PM1_EC_CTRL21_REG_OFS 0x0106u 85 #define MCHP_ACPI_PM1_CTRL21_REG_MASK 0u 86 87 /* ACPI_PM1 RT/EC Control 22 */ 88 #define MCHP_ACPI_PM1_RT_CTRL22_REG_OFS 7u 89 #define MCHP_ACPI_PM1_EC_CTRL22_REG_OFS 0x0107u 90 #define MCHP_ACPI_PM1_CTRL22_REG_MASK 0u 91 92 /* ACPI_PM1 EC PM Status register */ 93 #define MCHP_ACPI_PM1_EC_PM_STS_REG_OFS 0x0110u 94 #define MCHP_ACPI_PM1_EC_PM_STS_REG_MASK 0x01u 95 #define MCHP_ACPI_PM1_EC_PM_STS_SCI 0x01u 96 97 /** @brief ACPI EC Registers (ACPI_EC) */ 98 struct acpi_ec_regs { 99 volatile uint32_t OS_DATA; 100 volatile uint8_t OS_CMD_STS; 101 volatile uint8_t OS_BYTE_CTRL; 102 uint8_t RSVD1[0x100u - 0x06u]; 103 volatile uint32_t EC2OS_DATA; 104 volatile uint8_t EC_STS; 105 volatile uint8_t EC_BYTE_CTRL; 106 uint8_t RSVD2[2]; 107 volatile uint32_t OS2EC_DATA; 108 }; 109 110 /** @brief ACPI PM1 Registers (ACPI_PM1) */ 111 struct acpi_pm1_regs { 112 volatile uint8_t RT_STS1; 113 volatile uint8_t RT_STS2; 114 volatile uint8_t RT_EN1; 115 volatile uint8_t RT_EN2; 116 volatile uint8_t RT_CTRL1; 117 volatile uint8_t RT_CTRL2; 118 volatile uint8_t RT_CTRL21; 119 volatile uint8_t RT_CTRL22; 120 uint8_t RSVD1[(0x100u - 0x008u)]; 121 volatile uint8_t EC_STS1; 122 volatile uint8_t EC_STS2; 123 volatile uint8_t EC_EN1; 124 volatile uint8_t EC_EN2; 125 volatile uint8_t EC_CTRL1; 126 volatile uint8_t EC_CTRL2; 127 volatile uint8_t EC_CTRL21; 128 volatile uint8_t EC_CTRL22; 129 uint8_t RSVD2[(0x0110u - 0x0108u)]; 130 volatile uint8_t EC_PM_STS; 131 uint8_t RSVD3[3]; 132 }; 133 134 #endif /* #ifndef _MEC_ACPI_EC_H */ 135
