1# Copyright 2023 The ChromiumOS Authors
2# SPDX-License-Identifier: Apache-2.0
3
4orsource "*/Kconfig.defconfig"
5
6if SOC_FAMILY_MTK
7
8config INTC_MTK_ADSP
9	default y
10
11config XTENSA_SMALL_VECTOR_TABLE_ENTRY
12	default y
13
14config XTENSA_USE_CORE_CRT1
15	default n
16
17config MULTI_LEVEL_INTERRUPTS
18	default y
19config 2ND_LEVEL_INTERRUPTS
20	default y
21config MAX_IRQ_PER_AGGREGATOR
22	default 32
23config 2ND_LVL_ISR_TBL_OFFSET
24	default 32
25
26# The 8186/8188 core has only one software interrupt that lives at
27# level 2, underneath other hardware interrupts like timer, so it
28# can't reliably do this.  Unselect so the tests don't try to exercise
29# it.
30config IRQ_OFFLOAD_NESTED
31	default n if SOC_SERIES_MT818X
32	default y
33
34config MTK_ADSP_TIMER
35	default y
36config XTENSA_TIMER
37	default n
38
39config XTENSA_CCOUNT_HZ
40	default 720000000 if SOC_MT8195
41	default 400000000 if SOC_MT8186
42	default 800000000 if SOC_MT8188
43	default 800000000 if SOC_MT8196
44
45config SYS_CLOCK_HW_CYCLES_PER_SEC
46	default $(dt_node_int_prop_int,$(dt_nodelabel_path,ostimer64),freq-hz)
47
48config MAIN_STACK_SIZE
49	default 2048
50
51# This platform has a single big DRAM region where most linkage
52# happens.  The libc heap normally wants to steal all of it, when in
53# fact SOF has its own heap.  Just leave a little for stray malloc()
54# calls to find.
55config COMMON_LIBC_MALLOC_ARENA_SIZE
56	default 32768
57
58# Don't build the HAL if the toolchain already includes it.  Note that
59# this is done in the SOC layer historically, really this belongs in
60# arch/xtensa or the toolchain integration.
61#
62config XTENSA_HAL
63	default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc"
64	default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang"
65	default y
66
67config SOC_TOOLCHAIN_NAME
68	default "mtk_mt8195_adsp" if SOC_SERIES_MT8195
69	default "mtk_mt818x_adsp" if SOC_SERIES_MT818X
70	default "mtk_mt8196_adsp" if SOC_SERIES_MT8196
71
72config XTENSA_RESET_VECTOR
73	default n
74
75# This single-core device doesn't have S32C1I and so has no built-in
76# atomics.  Note we must disable _ARCH explicitly because
77# CONFIG_XTENSA turns it on (due to an xcc lack of gcc builtins?)
78#
79config ATOMIC_OPERATIONS_C
80	default y
81config ATOMIC_OPERATIONS_ARCH
82	default n
83
84config GEN_ISR_TABLES
85	default y
86config GEN_SW_ISR_TABLE
87	default y
88config GEN_IRQ_VECTOR_TABLE
89	default n
90
91endif # SOC_FAMILY_MTK
92