1 /* 2 * Copyright (c) 2021 ITE Corporation. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/device.h> 8 #include <soc.h> 9 10 /* SMFI register structure check */ 11 IT8XXX2_REG_SIZE_CHECK(smfi_it8xxx2_regs, 0xd1); 12 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_ECINDAR0, 0x3b); 13 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_ECINDAR1, 0x3c); 14 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_ECINDAR2, 0x3d); 15 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_ECINDAR3, 0x3e); 16 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_ECINDDR, 0x3f); 17 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_SCAR0L, 0x40); 18 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_SCAR0M, 0x41); 19 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_SCAR0H, 0x42); 20 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_HRAMWC, 0x5a); 21 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_HRAMW0BA, 0x5b); 22 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_HRAMW1BA, 0x5c); 23 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_HRAMW0AAS, 0x5d); 24 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_HRAMW1AAS, 0x5e); 25 IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_FLHCTRL6R, 0xa2); 26 27 /* EC2I register structure check */ 28 IT8XXX2_REG_SIZE_CHECK(ec2i_regs, 0x06); 29 IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IHIOA, 0x00); 30 IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IHD, 0x01); 31 IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, LSIOHA, 0x02); 32 IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IBMAE, 0x04); 33 IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IBCTL, 0x05); 34 35 /* KBC register structure check */ 36 IT8XXX2_REG_SIZE_CHECK(kbc_regs, 0x0b); 37 IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHICR, 0x00); 38 IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBIRQR, 0x02); 39 IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHISR, 0x04); 40 IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHIKDOR, 0x06); 41 IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHIMDOR, 0x08); 42 IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHIDIR, 0x0a); 43 44 /* PMC register structure check */ 45 IT8XXX2_REG_SIZE_CHECK(pmc_regs, 0x100); 46 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1STS, 0x00); 47 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1DO, 0x01); 48 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1DI, 0x04); 49 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1CTL, 0x06); 50 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2STS, 0x10); 51 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2DO, 0x11); 52 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2DI, 0x14); 53 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2CTL, 0x16); 54 IT8XXX2_REG_OFFSET_CHECK(pmc_regs, MBXCTRL, 0x19); 55 56 /* eSPI slave register structure check */ 57 IT8XXX2_REG_SIZE_CHECK(espi_slave_regs, 0xd8); 58 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, GCAPCFG1, 0x05); 59 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_PC_CAPCFG3, 0x0b); 60 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_VW_CAPCFG3, 0x0f); 61 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_OOB_CAPCFG3, 0x13); 62 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_FLASH_CAPCFG3, 0x17); 63 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_FLASH_CAPCFG2_3, 0x1b); 64 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESPCTRL0, 0x90); 65 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL0, 0xa0); 66 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL1, 0xa1); 67 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL2, 0xa2); 68 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESUCTRL0, 0xb0); 69 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESOCTRL0, 0xc0); 70 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESOCTRL1, 0xc1); 71 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESPISAFSC0, 0xd0); 72 IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESPISAFSC7, 0xd7); 73 74 /* eSPI vw register structure check */ 75 IT8XXX2_REG_SIZE_CHECK(espi_vw_regs, 0x9a); 76 IT8XXX2_REG_OFFSET_CHECK(espi_vw_regs, VW_INDEX, 0x00); 77 IT8XXX2_REG_OFFSET_CHECK(espi_vw_regs, VWCTRL0, 0x90); 78 IT8XXX2_REG_OFFSET_CHECK(espi_vw_regs, VWCTRL1, 0x91); 79 80 /* eSPI Queue 0 registers structure check */ 81 IT8XXX2_REG_SIZE_CHECK(espi_queue0_regs, 0xd0); 82 IT8XXX2_REG_OFFSET_CHECK(espi_queue0_regs, PUT_OOB_DATA, 0x80); 83 84 /* eSPI Queue 1 registers structure check */ 85 IT8XXX2_REG_SIZE_CHECK(espi_queue1_regs, 0xc0); 86 IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, UPSTREAM_DATA, 0x00); 87 IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, PUT_FLASH_NP_DATA, 0x80); 88 89 /* GPIO register structure check */ 90 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 91 IT8XXX2_REG_SIZE_CHECK(gpio_it8xxx2_regs, 0x100); 92 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR, 0x00); 93 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR31, 0xD5); 94 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR18, 0xE2); 95 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR21, 0xE6); 96 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR29, 0xEE); 97 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR2, 0xF1); 98 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR7, 0xF6); 99 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR14, 0xFD); 100 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 101 IT8XXX2_REG_SIZE_CHECK(gpio_it8xxx2_regs, 0x2f); 102 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR, 0x00); 103 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR2, 0x11); 104 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR7, 0x16); 105 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR12, 0x1b); 106 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_PGWCR, 0x1f); 107 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR21, 0x26); 108 IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR30, 0x2d); 109 #endif 110 111 /* GCTRL register structure check */ 112 IT8XXX2_REG_SIZE_CHECK(gctrl_it8xxx2_regs, 0x88); 113 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RSTS, 0x06); 114 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_BADRSEL, 0x0a); 115 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_WNCKR, 0x0b); 116 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_SPCTRL1, 0x0d); 117 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_SPCTRL4, 0x1c); 118 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RSTC5, 0x21); 119 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, gctrl_pmer2, 0x33); 120 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_EPLR, 0x37); 121 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_IVTBAR, 0x41); 122 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_MCCR2, 0x44); 123 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_P80H81HSR, 0x50); 124 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_P80HDR, 0x51); 125 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_H2ROFSR, 0x53); 126 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RVILMCR0, 0x5D); 127 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_ECHIPID2, 0x86); 128 IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_ECHIPID3, 0x87); 129 130 /* PECI register structure check */ 131 IT8XXX2_REG_SIZE_CHECK(peci_it8xxx2_regs, 0x0F); 132 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOSTAR, 0x00); 133 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOCTLR, 0x01); 134 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOCMDR, 0x02); 135 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOTRADDR, 0x03); 136 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOWRLR, 0x04); 137 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HORDLR, 0x05); 138 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOWRDR, 0x06); 139 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HORDDR, 0x07); 140 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOCTL2R, 0x08); 141 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, RWFCSV, 0x09); 142 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, RRFCSV, 0x0A); 143 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, WFCSV, 0x0B); 144 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, RFCSV, 0x0C); 145 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, AWFCSV, 0x0D); 146 IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, PADCTLR, 0x0E); 147 148 /* USB Device register structure check */ 149 IT8XXX2_REG_SIZE_CHECK(usb_it82xx2_regs, 0xE9); 150 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_ctrl, 0x00); 151 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_trans_type, 0x01); 152 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_line_ctrl, 0x02); 153 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_sof_enable, 0x03); 154 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_addr, 0x04); 155 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_endp, 0x05); 156 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_frame_num_msp, 0x06); 157 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_frame_num_lsp, 0x07); 158 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_interrupt_status, 0x08); 159 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_interrupt_mask, 0x09); 160 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_status, 0x0A); 161 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_pid, 0x0B); 162 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, misc_control, 0x0C); 163 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, misc_status, 0x0D); 164 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_connect_state, 0x0E); 165 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_sof_timer_msb, 0x0F); 166 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_ctrl, 0x40); 167 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_status, 0x41); 168 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, 169 usb_ep_regs[EP0].ep_transtype_sts, 0x42); 170 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, 171 usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43); 172 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_ctrl, 0x4C); 173 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_status, 0x4D); 174 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, 175 usb_ep_regs[EP3].ep_transtype_sts, 0x4E); 176 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, 177 usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F); 178 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_control, 0x50); 179 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_frame_num_lsp, 0x56); 180 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_rx_fifo_data, 0x60); 181 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_tx_fifo_ctrl, 0x74); 182 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, 183 fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl, 0x98); 184 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, 185 fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8); 186 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, 187 fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6); 188 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_device_control, 0xE0); 189 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, port1_misc_control, 0xE8); 190 191 192 /* KSCAN register structure check */ 193 IT8XXX2_REG_SIZE_CHECK(kscan_it8xxx2_regs, 0x0F); 194 IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOL, 0x00); 195 IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOCTRL, 0x02); 196 IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSI, 0x04); 197 IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSIGDAT, 0x08); 198 IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOLGOEN, 0x0e); 199 200 /* ADC register structure check */ 201 IT8XXX2_REG_SIZE_CHECK(adc_it8xxx2_regs, 0xf1); 202 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, ADCGCR, 0x03); 203 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, VCH0DATM, 0x19); 204 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, ADCIVMFSCS1, 0x55); 205 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, ADCIVMFSCS2, 0x56); 206 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, ADCIVMFSCS3, 0x57); 207 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, adc_vchs_ctrl[0].VCHCTL, 0x60); 208 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, adc_vchs_ctrl[2].VCHDATM, 0x67); 209 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, ADCDVSTS2, 0x6c); 210 IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, ADCCTL1, 0xf0); 211 212 /* Watchdog register structure check */ 213 IT8XXX2_REG_SIZE_CHECK(wdt_it8xxx2_regs, 0x0f); 214 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ETWCFG, 0x01); 215 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1PSR, 0x02); 216 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1CNTLHR, 0x03); 217 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1CNTLLR, 0x04); 218 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ETWCTRL, 0x05); 219 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDCNTLR, 0x06); 220 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDKEYR, 0x07); 221 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDCNTHR, 0x09); 222 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2PSR, 0x0a); 223 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2CNTLHR, 0x0b); 224 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2CNTLLR, 0x0c); 225 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2CNTLH2R, 0x0e); 226 227 /* SPISC register structure check */ 228 IT8XXX2_REG_SIZE_CHECK(spisc_it8xxx2_regs, 0x28); 229 IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_IMR, 0x04); 230 IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_RXFSR, 0x07); 231 IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_CPUWTXFDB2R, 0x0a); 232 IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_RXFRDRB1, 0x0d); 233 IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_FTCB1R, 0x19); 234 IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_HPR2, 0x1e); 235 IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_RXVLISR, 0x27); 236 237 /* PWM register structure check */ 238 IT8XXX2_REG_SIZE_CHECK(pwm_it8xxx2_regs, 0x4a); 239 IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, C0CPRS, 0x00); 240 IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, CTR1M, 0x10); 241 IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, C4CPRS, 0x27); 242 IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, CTR2, 0x42); 243 IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, PWMODENR, 0x49); 244
