1 /* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or 2 * an affiliate of Cypress Semiconductor Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @brief Infineon CYW920829 soc. 9 */ 10 11 #include <zephyr/device.h> 12 #include <zephyr/init.h> 13 #include <zephyr/kernel.h> 14 15 #include <cy_sysint.h> 16 #include <system_cat1b.h> 17 #include "cy_pdl.h" 18 19 extern int ifx_pm_init(void); 20 Cy_SysInt_Init(const cy_stc_sysint_t * config,cy_israddress userIsr)21cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr) 22 { 23 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); 24 cy_en_sysint_status_t status = CY_SYSINT_SUCCESS; 25 26 /* The interrupt vector will be relocated only if the vector table was 27 * moved to SRAM (CONFIG_DYNAMIC_INTERRUPTS and CONFIG_GEN_ISR_TABLES 28 * must be enabled). Otherwise it is ignored. 29 */ 30 31 #if defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES) 32 if (config != NULL) { 33 uint32_t priority; 34 35 /* NOTE: 36 * PendSV IRQ (which is used in Cortex-M variants to implement thread 37 * context-switching) is assigned the lowest IRQ priority level. 38 * If priority is same as PendSV, we will catch assertion in 39 * z_arm_irq_priority_set function. To avoid this, change priority 40 * to IRQ_PRIO_LOWEST, if it > IRQ_PRIO_LOWEST. Macro IRQ_PRIO_LOWEST 41 * takes in to account PendSV specific. 42 */ 43 priority = (config->intrPriority > IRQ_PRIO_LOWEST) ? 44 IRQ_PRIO_LOWEST : config->intrPriority; 45 46 /* Configure a dynamic interrupt */ 47 (void) irq_connect_dynamic(config->intrSrc, priority, 48 (void *) userIsr, NULL, 0); 49 } else { 50 status = CY_SYSINT_BAD_PARAM; 51 } 52 #endif /* defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES) */ 53 54 return(status); 55 } 56 57 /* 58 * This function will allow execute from sram region. This is needed only for 59 * this sample because by default all soc will disable the execute from SRAM. 60 * An application that requires that the code be executed from SRAM will have 61 * to configure the region appropriately in arm_mpu_regions.c. 62 */ 63 #ifdef CONFIG_ARM_MPU 64 #include <cmsis_core.h> disable_mpu_rasr_xn(void)65void disable_mpu_rasr_xn(void) 66 { 67 uint32_t index; 68 69 /* 70 * Kept the max index as 8(irrespective of soc) because the sram would 71 * most likely be set at index 2. 72 */ 73 for (index = 0U; index < 8; index++) { 74 MPU->RNR = index; 75 #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) 76 if (MPU->RBAR & MPU_RBAR_XN_Msk) { 77 MPU->RBAR ^= MPU_RBAR_XN_Msk; 78 } 79 #else 80 if (MPU->RASR & MPU_RASR_XN_Msk) { 81 MPU->RASR ^= MPU_RASR_XN_Msk; 82 } 83 #endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */ 84 } 85 } 86 #endif /* CONFIG_ARM_MPU */ 87 soc_early_init_hook(void)88void soc_early_init_hook(void) 89 { 90 #ifdef CONFIG_ARM_MPU 91 disable_mpu_rasr_xn(); 92 #endif /* CONFIG_ARM_MPU */ 93 94 /* Initializes the system */ 95 SystemInit(); 96 97 #ifdef CONFIG_PM 98 ifx_pm_init(); 99 #endif 100 } 101
