1 /*
2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "soc.h"
8
9 /*
10 * Instruction Cache definitions
11 */
12 #if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB)
13 #define ESP32S2_ICACHE_SIZE CACHE_SIZE_8KB
14 #else
15 #define ESP32S2_ICACHE_SIZE CACHE_SIZE_16KB
16 #endif
17
18 #if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B)
19 #define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
20 #else
21 #define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
22 #endif
23
24 /*
25 * Data Cache definitions
26 */
27 #if defined(CONFIG_ESP32S2_DATA_CACHE_0KB)
28 #define ESP32S2_DCACHE_SIZE CACHE_SIZE_0KB
29 #elif defined(CONFIG_ESP32S2_DATA_CACHE_8KB)
30 #define ESP32S2_DCACHE_SIZE CACHE_SIZE_8KB
31 #else
32 #define ESP32S2_DCACHE_SIZE CACHE_SIZE_16KB
33 #endif
34
35 #if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B)
36 #define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
37 #else
38 #define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
39 #endif
40
esp_config_instruction_cache_mode(void)41 void IRAM_ATTR esp_config_instruction_cache_mode(void)
42 {
43 cache_size_t cache_size;
44 cache_ways_t cache_ways;
45 cache_line_size_t cache_line_size;
46
47 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
48 esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,
49 CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
50 #else
51 esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
52 CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
53 #endif
54 cache_size = ESP32S2_ICACHE_SIZE;
55 cache_ways = CACHE_4WAYS_ASSOC;
56 cache_line_size = ESP32S2_ICACHE_LINE_SIZE;
57
58 esp_rom_Cache_Suspend_ICache();
59 esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
60 esp_rom_Cache_Invalidate_ICache_All();
61 esp_rom_Cache_Resume_ICache(0);
62 }
63
esp_config_data_cache_mode(void)64 void IRAM_ATTR esp_config_data_cache_mode(void)
65 {
66 cache_size_t cache_size;
67 cache_ways_t cache_ways;
68 cache_line_size_t cache_line_size;
69
70 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
71 #if CONFIG_ESP32S2_DATA_CACHE_0KB
72 Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID,
73 CACHE_MEMORY_INVALID);
74 #elif CONFIG_ESP32S2_DATA_CACHE_8KB
75 esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
76 CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
77 #else
78 esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
79 CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
80 #endif
81 #else
82 #if CONFIG_ESP32S2_DATA_CACHE_0KB
83 Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID,
84 CACHE_MEMORY_INVALID);
85 #elif CONFIG_ESP32S2_DATA_CACHE_8KB
86 esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
87 CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
88 #else
89 esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
90 CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
91 #endif
92 #endif
93 cache_size = ESP32S2_DCACHE_SIZE;
94 cache_ways = CACHE_4WAYS_ASSOC;
95 cache_line_size = ESP32S2_DCACHE_LINE_SIZE;
96
97 esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
98 esp_rom_Cache_Invalidate_DCache_All();
99 }
100
