1/* Copyright 2023 Espressif Systems (Shanghai) PTE LTD
2 *
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include "soc/soc.h"
7#include "soc/interrupt_reg.h"
8#include "riscv/rvruntime-frames.h"
9#include "soc/soc_caps.h"
10#include <zephyr/toolchain.h>
11
12/* Imports */
13GTEXT(_isr_wrapper)
14
15	/* This is the vector table. MTVEC points here.
16	 *
17	 * Use 4-byte intructions here. 1 instruction = 1 entry of the table.
18	 * The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
19	 * and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
20	 *
21	 * Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
22	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
23	 */
24
25	.global  _esp32c6_vector_table
26	.section .exception_vectors.text
27	.balign   0x100
28	.type     _esp32c6_vector_table, @function
29
30_esp32c6_vector_table:
31	.option push
32	.option norvc
33	.rept (32)
34	j _isr_wrapper		/* 32 identical entries, all pointing to the interrupt handler */
35	.endr
36