1# Copyright (c) 2016 Open-RnD Sp. z o.o.
2# Copyright (c) 2016 Cadence Design Systems, Inc.
3# Copyright (c) 2023 Intel Corporation
4#
5# SPDX-License-Identifier: Apache-2.0
6
7if SOC_XTENSA_DC233C
8
9config SOC_XTENSA_DC233C
10	select XTENSA_GEN_HANDLERS
11
12config XTENSA_MMU_NUM_L2_TABLES
13	int
14	default 48 if XTENSA_MMU
15
16# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB.
17# This is to allow VECBASE to be mapped permanently
18# via TLB way 4 (which covers 1MB).
19config SRAM_OFFSET
20	hex
21	default 0x100000 if XTENSA_MMU
22	default 0x2400
23
24config KERNEL_VM_OFFSET
25	hex
26	default 0x100000
27
28endif
29