1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	aliases {
9		sram-ext = &aps6404l;
10	};
11};
12
13&w25q512jvfiq {
14	/*
15	 * Lower max FlexSPI frequency to 109MHz, as the PSRAM does not support
16	 * higher frequencies at 3.3V
17	 */
18	spi-max-frequency = <109000000>;
19};
20
21&aps6404l {
22	status = "okay";
23};
24
25&pinctrl {
26	pinmux_flexspi_safe: pinmux-flexspi-safe {
27		group0 {
28			pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO35
29				IO_MUX_QUAD_SPI_PSRAM_IO36
30				IO_MUX_QUAD_SPI_PSRAM_IO38
31				IO_MUX_QUAD_SPI_PSRAM_IO39
32				IO_MUX_QUAD_SPI_PSRAM_IO40
33				IO_MUX_QUAD_SPI_PSRAM_IO41>;
34			slew-rate = "normal";
35		};
36
37		group1 {
38			pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO37>;
39			slew-rate = "normal";
40			bias-pull-down;
41		};
42	};
43};
44
45/* Override pin control state to use one that only changes the PSRAM pin
46 * configuration
47 */
48&flexspi {
49	pinctrl-0 = <&pinmux_flexspi_safe>;
50	pinctrl-names = "default";
51};
52