1 /*
2  * Copyright (c) 2018 Intel Corporation.
3  * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #include <zephyr/kernel.h>
9 #include <zephyr/sys/printk.h>
10 
11 /*
12  * This function will allow execute from sram region.  This is needed only for
13  * this sample because by default all soc will disable the execute from SRAM.
14  * An application that requires that the code be executed from SRAM will have
15  * to configure the region appropriately in arm_mpu_regions.c.
16  */
17 #ifdef CONFIG_ARM_MPU
18 #include <cmsis_core.h>
disable_mpu_rasr_xn(void)19 void disable_mpu_rasr_xn(void)
20 {
21 	uint32_t index;
22 
23 	/*
24 	 * Kept the max index as 8(irrespective of soc) because the sram would
25 	 * most likely be set at index 2.
26 	 */
27 	for (index = 0U; index < 8; index++) {
28 		MPU->RNR = index;
29 #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
30 		if (MPU->RBAR & MPU_RBAR_XN_Msk) {
31 			MPU->RBAR ^= MPU_RBAR_XN_Msk;
32 		}
33 #else
34 		if (MPU->RASR & MPU_RASR_XN_Msk) {
35 			MPU->RASR ^= MPU_RASR_XN_Msk;
36 		}
37 #endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */
38 	}
39 }
40 #endif /* CONFIG_ARM_MPU */
41 
42 extern void function_in_ext_flash(void);
43 extern void function_in_sram(void);
44 
main(void)45 int main(void)
46 {
47 #ifdef CONFIG_ARM_MPU
48 	disable_mpu_rasr_xn();
49 #endif	/* CONFIG_ARM_MPU */
50 
51 	printk("Address of %s function %p\n", __func__, &main);
52 
53 	function_in_ext_flash();
54 	function_in_sram();
55 
56 	printk("Hello World! %s\n", CONFIG_BOARD);
57 	return 0;
58 }
59