1 /*
2  * Copyright (c) 2022 Google Inc
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_
9 
10 #include "stm32-common.h"
11 
12 /* RCC bus reset register offset */
13 #define STM32_RESET_BUS_AHB1  0x80
14 #define STM32_RESET_BUS_AHB2  0x84
15 #define STM32_RESET_BUS_AHB3  0x7C
16 #define STM32_RESET_BUS_AHB4  0x88
17 #define STM32_RESET_BUS_APB1L 0x90
18 #define STM32_RESET_BUS_APB1H 0x94
19 #define STM32_RESET_BUS_APB2  0x98
20 #define STM32_RESET_BUS_APB3  0x8C
21 #define STM32_RESET_BUS_APB4  0x9C
22 
23 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_ */
24