1 /* 2 * Copyright (c) 2024 Andrew Featherstone 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ 9 10 #define RPI_PICO_RESETS_RESET_ADC 0 11 #define RPI_PICO_RESETS_RESET_BUSCTRL 1 12 #define RPI_PICO_RESETS_RESET_DMA 2 13 #define RPI_PICO_RESETS_RESET_HSTX 3 14 #define RPI_PICO_RESETS_RESET_I2C0 4 15 #define RPI_PICO_RESETS_RESET_I2C1 5 16 #define RPI_PICO_RESETS_RESET_IO_BANK0 6 17 #define RPI_PICO_RESETS_RESET_IO_QSPI 7 18 #define RPI_PICO_RESETS_RESET_JTAG 8 19 #define RPI_PICO_RESETS_RESET_PADS_BANK0 9 20 #define RPI_PICO_RESETS_RESET_PADS_QSPI 10 21 #define RPI_PICO_RESETS_RESET_PIO0 11 22 #define RPI_PICO_RESETS_RESET_PIO1 12 23 #define RPI_PICO_RESETS_RESET_PIO2 13 24 #define RPI_PICO_RESETS_RESET_PLL_SYS 14 25 #define RPI_PICO_RESETS_RESET_PLL_USB 15 26 #define RPI_PICO_RESETS_RESET_PWM 16 27 #define RPI_PICO_RESETS_RESET_SHA256 17 28 #define RPI_PICO_RESETS_RESET_SPI0 18 29 #define RPI_PICO_RESETS_RESET_SPI1 19 30 #define RPI_PICO_RESETS_RESET_SYSCFG 20 31 #define RPI_PICO_RESETS_RESET_SYSINFO 21 32 #define RPI_PICO_RESETS_RESET_TBMAN 22 33 #define RPI_PICO_RESETS_RESET_TIMER0 23 34 #define RPI_PICO_RESETS_RESET_TIMER1 24 35 #define RPI_PICO_RESETS_RESET_TRNG 25 36 #define RPI_PICO_RESETS_RESET_UART0 26 37 #define RPI_PICO_RESETS_RESET_UART1 27 38 #define RPI_PICO_RESETS_RESET_USBCTRL 28 39 40 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ */ 41
