1 /*
2  * Copyright (c) 2019 Intel Corp.
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXPCEPTION_H_
7 #define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXPCEPTION_H_
8 
9 #ifndef _ASMLANGUAGE
10 #include <zephyr/arch/x86/intel64/thread.h>
11 
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15 
16 /*
17  * the exception stack frame
18  */
19 
20 struct arch_esf {
21 #ifdef CONFIG_EXCEPTION_DEBUG
22 	/* callee-saved */
23 	unsigned long rbx;
24 	unsigned long r12;
25 	unsigned long r13;
26 	unsigned long r14;
27 	unsigned long r15;
28 #endif /* CONFIG_EXCEPTION_DEBUG */
29 	unsigned long rbp;
30 
31 	/* Caller-saved regs */
32 	unsigned long rax;
33 	unsigned long rcx;
34 	unsigned long rdx;
35 	unsigned long rsi;
36 	unsigned long rdi;
37 	unsigned long r8;
38 	unsigned long r9;
39 	unsigned long r10;
40 	/* Must be aligned 16 bytes from the end of this struct due to
41 	 * requirements of 'fxsave (%rsp)'
42 	 */
43 	char fxsave[X86_FXSAVE_SIZE];
44 	unsigned long r11;
45 
46 	/* Pushed by CPU or assembly stub */
47 	unsigned long vector;
48 	unsigned long code;
49 	unsigned long rip;
50 	unsigned long cs;
51 	unsigned long rflags;
52 	unsigned long rsp;
53 	unsigned long ss;
54 };
55 
56 struct x86_ssf {
57 	unsigned long rip;
58 	unsigned long rflags;
59 	unsigned long r10;
60 	unsigned long r9;
61 	unsigned long r8;
62 	unsigned long rdx;
63 	unsigned long rsi;
64 	char fxsave[X86_FXSAVE_SIZE];
65 	unsigned long rdi;
66 	unsigned long rsp;
67 };
68 
69 #ifdef __cplusplus
70 }
71 #endif
72 
73 #endif /* _ASMLANGUAGE */
74 
75 #endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXPCEPTION_H_ */
76