1# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
2# Copyright (c) 2022, NXP
3# SPDX-License-Identifier: Apache-2.0
4
5description: |
6  OpenISA RV32M1 Pin Controller
7
8  This node will define pin configurations in pin groups,
9  and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
10  within the pin configuration defines the pin configuration for a peripheral,
11  and each numbered subgroup in the pin group defines all the pins for that
12  peripheral with the same configuration properties. The 'pins' property in
13  a group selects the pins to be configured, and the remaining properties set
14  configuration values for those pins. Here is an example group for UART0 pins:
15
16  uart0_default: uart0_default {
17    group0 {
18      pinmux = <RV32M1_MUX('C', 7, 3)>,
19               <RV32M1_MUX('C', 8, 3)>;
20      drive-strength = "low";
21      slew-rate = "fast";
22    };
23  };
24
25  If only the required properties are supplied, the pin configuration register
26  will be assigned the following values:
27  PCR_PS=0,
28  PCR_PE=0,
29  PCR_ODE=0,
30  PCR_SRE=<slew-rate selection>,
31  PCR_PFE=0
32
33compatible: "openisa,rv32m1-pinctrl"
34
35include: base.yaml
36
37child-binding:
38  description: RV32M1 pin controller pin group
39  child-binding:
40    description: |
41      RV31M1 pin controller pin configuration node
42
43    include:
44      - name: pincfg-node.yaml
45        property-allowlist:
46          - drive-open-drain
47          - bias-pull-up
48          - bias-pull-down
49
50    properties:
51      pinmux:
52        required: true
53        type: array
54        description: |
55          Pin mux selections for this group. See the SoC level pinctrl DTSI file
56          in the OpenISA HAL for a defined list of these options
57      slew-rate:
58        required: true
59        type: string
60        enum:
61          - "fast"
62          - "slow"
63        description: |
64          Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
65          0 SRE_0_fast- fast slew rate when pin is configured as output
66          1 SRE_1_slow- slow slew rate when pin is configured as output
67      openisa,passive-filter:
68        type: boolean
69        description: |
70          Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.
71