1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Main PLL node binding for STM32F0 and STM32F3 devices.
6
7  Takes one of clk_hse or clk_hsi as input clock.
8
9  Note: Some STM32F0 SoC variants (STM32072 for instance) may also support HSI48
10  as input clock. This case is not supported yet.
11
12  Frequency calculation for output clock is as follows:
13
14    f(PLLCLK) = f(PLLIN) x PLLMUL   --> SYSCLK (System Clock)
15
16    with, depending on the case:
17            If input_clk = clk_hse
18              f(PLLIN) = f(input_clk) / PREDIV
19            If input_clk = clk_hsi
20              On STM32F3, STM32F03x, STM32F05x, STM32F030x4, STM32F030x6 and STM32F030x8
21                f(PLLIN) = f(input_clk) / 2
22              On STM32F04x, STM32F07x, STM32F09x, STM32F070x6, STM32F070xB and STM32F030xC
23                f(PLLIN) = f(input_clk) / PREDIV
24
25  The PLL output frequency must be set in range 16-48MHz
26
27compatible: "st,stm32f0-pll-clock"
28
29include:
30  - name: st,stm32f105-pll-clock.yaml
31    property-blocklist:
32      - mul
33      - otgfspre
34
35properties:
36  mul:
37    type: int
38    required: true
39    description: |
40        PLL multiplication factor for output clock
41        Valid range: 2 - 16
42