1/*
2 * Copyright (c) 2020 Jonas Eriksson, Up to Code AB
3 *
4 * SoC device tree include for STM32F100xE SoCs
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#include <mem.h>
10#include <st/f1/stm32f100Xb.dtsi>
11
12/ {
13	sram0: memory@20000000 {
14		reg = <0x20000000 DT_SIZE_K(32)>;
15	};
16
17	soc {
18		flash-controller@40022000 {
19			flash0: flash@8000000 {
20				reg = <0x08000000 DT_SIZE_K(512)>;
21			};
22		};
23
24		spi3: spi@40003c00 {
25			compatible = "st,stm32-spi";
26			#address-cells = <1>;
27			#size-cells = <0>;
28			reg = <0x40003c00 0x400>;
29			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
30			interrupts = <51 5>;
31			status = "disabled";
32		};
33	};
34};
35