1/*
2 * Copyright 2021,2023-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/power/imx_spc.h>
15#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
16/ {
17	chosen {
18		zephyr,entropy = &caam;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m7";
28			reg = <0>;
29
30			#address-cells = <1>;
31			#size-cells = <1>;
32			d-cache-line-size = <32>;
33
34			mpu: mpu@e000ed90 {
35				compatible = "arm,armv7m-mpu";
36				reg = <0xe000ed90 0x40>;
37			};
38		};
39		cpu1: cpu@1 {
40			device_type = "cpu";
41			compatible = "arm,cortex-m4f";
42			reg = <1>;
43			d-cache-line-size = <32>;
44
45			#address-cells = <1>;
46			#size-cells = <1>;
47
48			mpu: mpu@e000ed90 {
49				compatible = "arm,armv7m-mpu";
50				reg = <0xe000ed90 0x40>;
51			};
52		};
53
54		power-states {
55			/*
56			 * Power states are managed with set points (see page 30-35 of RT1170
57			 * datasheet). These set points correspond to various power
58			 * savings, and associated transition (residency) times.
59			 *
60			 * Set points 1 and 10 were chosen as sane defaults to offer
61			 * limited power savings and quick transitions when entering idle for
62			 * short periods, and better power savings with longer transition
63			 * times for long idle periods
64			 */
65			idle: set_point_1_wait {
66				/* idle corresponds to set point 1 (wait) for RT1170 */
67				compatible = "zephyr,power-state";
68				power-state-name="runtime-idle";
69				substate-id = <IMX_SPC_SET_POINT_1_WAIT>;
70				min-residency-us = <100>;
71			};
72
73			suspend: set_point_10_suspend {
74				/*  suspend corresponds to set point 10 for RT1170 */
75				compatible = "zephyr,power-state";
76				power-state-name="suspend-to-idle";
77				substate-id = <IMX_SPC_SET_POINT_10_SUSPEND>;
78				min-residency-us = <5000>;
79				exit-latency-us = <500>;
80			};
81		};
82	};
83
84	xtal: xtal-osc {
85		compatible = "fixed-clock";
86		clock-frequency = <24000000>;
87		#clock-cells = <0>;
88	};
89
90	soc {
91		flexspi: spi@400cc000 {
92			compatible = "nxp,imx-flexspi";
93			reg = <0x400cc000 0x4000>;
94			interrupts = <130 0>;
95			#address-cells = <1>;
96			#size-cells = <0>;
97			status = "disabled";
98			clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
99		};
100
101		flexspi2: spi@400d0000 {
102			compatible = "nxp,imx-flexspi";
103			reg = <0x400d0000 0x4000>;
104			interrupts = <131 0>;
105			#address-cells = <1>;
106			#size-cells = <0>;
107			status = "disabled";
108			clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0>;
109		};
110
111		semc: semc0@400d4000 {
112			compatible = "nxp,imx-semc";
113			reg = <0x400d4000 0x4000>;
114			interrupts = <132 0>;
115			#address-cells = <1>;
116			#size-cells = <1>;
117		};
118
119		/* GPT1 is used for the hardware timer, not as a standard counter */
120		gpt_hw_timer: gpt@400ec000 {
121			compatible = "nxp,gpt-hw-timer";
122			reg = <0x400ec000 0x4000>;
123			interrupts = <119 0>;
124			status = "disabled";
125		};
126
127		gpt2: gpt@400f0000 {
128			compatible = "nxp,imx-gpt";
129			reg = <0x400f0000 0x4000>;
130			interrupts = <120 0>;
131			gptfreq = <24000000>;
132			clocks = <&ccm IMX_CCM_GPT_CLK 0x41 0>;
133		};
134
135		gpt3: gpt@400f4000 {
136			compatible = "nxp,imx-gpt";
137			reg = <0x400f4000 0x4000>;
138			interrupts = <121 0>;
139			gptfreq = <24000000>;
140			clocks = <&ccm IMX_CCM_GPT_CLK 0x42 0>;
141		};
142
143		gpt4: gpt@400f8000 {
144			compatible = "nxp,imx-gpt";
145			reg = <0x400f8000 0x4000>;
146			interrupts = <122 0>;
147			gptfreq = <24000000>;
148			clocks = <&ccm IMX_CCM_GPT_CLK 0x43 0>;
149		};
150
151		gpt5: gpt@400fc000 {
152			compatible = "nxp,imx-gpt";
153			reg = <0x400fc000 0x4000>;
154			interrupts = <123 0>;
155			gptfreq = <24000000>;
156			clocks = <&ccm IMX_CCM_GPT_CLK 0x44 0>;
157		};
158
159		gpt6: gpt@40100000 {
160			compatible = "nxp,imx-gpt";
161			reg = <0x40100000 0x4000>;
162			interrupts = <124 0>;
163			gptfreq = <24000000>;
164			clocks = <&ccm IMX_CCM_GPT_CLK 0x45 0>;
165		};
166
167		qtmr1: qtmr@4015c000 {
168			compatible = "nxp,qtmr-pwm";
169			reg = <0x4015c000 0x4000>;
170			interrupts = <171 0>;
171			status = "disabled";
172			clocks = <&ccm IMX_CCM_QTMR1_CLK 0x0 0>;
173		};
174
175		qtmr2: qtmr@40160000 {
176			compatible = "nxp,qtmr-pwm";
177			reg = <0x40160000 0x4000>;
178			interrupts = <172 0>;
179			status = "disabled";
180			clocks = <&ccm IMX_CCM_QTMR2_CLK 0x0 0>;
181		};
182
183		qtmr3: qtmr@40164000 {
184			compatible = "nxp,qtmr-pwm";
185			reg = <0x40164000 0x4000>;
186			interrupts = <173 0>;
187			status = "disabled";
188			clocks = <&ccm IMX_CCM_QTMR3_CLK 0x0 0>;
189		};
190
191		qtmr4: qtmr@40168000 {
192			compatible = "nxp,qtmr-pwm";
193			reg = <0x40168000 0x4000>;
194			interrupts = <174 0>;
195			status = "disabled";
196			clocks = <&ccm IMX_CCM_QTMR4_CLK 0x0 0>;
197		};
198
199		ccm: ccm@40cc0000 {
200			compatible = "nxp,imx-ccm-rev2";
201			reg = <0x40cc0000 0x4000>;
202
203			#clock-cells = <3>;
204
205			/*
206			 * ARM PLL is an integer PLL, with an input clock
207			 * of 24MHz. The PLL features a loop divider and
208			 * post divider. The output frequency is calculated
209			 * as Fout = 24MHz * (clock-mult / clock-div)
210			 */
211			arm_pll: arm-pll {
212				compatible = "fixed-factor-clock";
213				#clock-cells = <0>;
214			};
215
216		};
217
218		gpio1: gpio@4012c000 {
219			compatible = "nxp,imx-gpio";
220			reg = <0x4012c000 0x4000>;
221			interrupts = <100 0>, <101 0>;
222			gpio-controller;
223			#gpio-cells = <2>;
224		};
225
226		/*
227		 * Note that CM7 and CM4 cores do not have the same memory addresses
228		 * for GPIO2 and GPIO3, so those peripherals are defined in the SOC
229		 * specific DTS files
230		 */
231
232		gpio4: gpio@40138000 {
233			compatible = "nxp,imx-gpio";
234			reg = <0x40138000 0x4000>;
235			interrupts = <106 0>, <107 0>;
236			gpio-controller;
237			#gpio-cells = <2>;
238		};
239
240		gpio5: gpio@4013c000 {
241			compatible = "nxp,imx-gpio";
242			reg = <0x4013c000 0x4000>;
243			interrupts = <108 0>, <109 0>;
244			gpio-controller;
245			#gpio-cells = <2>;
246		};
247
248		gpio6: gpio@40140000 {
249			compatible = "nxp,imx-gpio";
250			reg = <0x40140000 0x4000>;
251			gpio-controller;
252			#gpio-cells = <2>;
253		};
254
255		gpio7: gpio@40c5c000 {
256			compatible = "nxp,imx-gpio";
257			reg = <0x40c5c000 0x4000>;
258			gpio-controller;
259			#gpio-cells = <2>;
260		};
261
262		gpio8: gpio@40c60000 {
263			compatible = "nxp,imx-gpio";
264			reg = <0x40c60000 0x4000>;
265			gpio-controller;
266			#gpio-cells = <2>;
267		};
268
269		gpio9: gpio@40c64000 {
270			compatible = "nxp,imx-gpio";
271			reg = <0x40c64000 0x4000>;
272			gpio-controller;
273			#gpio-cells = <2>;
274		};
275
276		gpio10: gpio@40c68000 {
277			compatible = "nxp,imx-gpio";
278			reg = <0x40c68000 0x4000>;
279			gpio-controller;
280			#gpio-cells = <2>;
281		};
282
283		gpio11: gpio@40c6c000 {
284			compatible = "nxp,imx-gpio";
285			reg = <0x40c6c000 0x4000>;
286			gpio-controller;
287			#gpio-cells = <2>;
288		};
289
290		gpio12: gpio@40c70000 {
291			compatible = "nxp,imx-gpio";
292			reg = <0x40c70000 0x4000>;
293			gpio-controller;
294			#gpio-cells = <2>;
295		};
296
297		gpio13: gpio@40ca0000 {
298			compatible = "nxp,imx-gpio";
299			reg = <0x40ca0000 0x4000>;
300			interrupts = <93 0>;
301			gpio-controller;
302			#gpio-cells = <2>;
303		};
304
305		lpi2c1: i2c@40104000 {
306			compatible = "nxp,lpi2c";
307			clock-frequency = <I2C_BITRATE_STANDARD>;
308			#address-cells = <1>;
309			#size-cells = <0>;
310			reg = <0x40104000 0x4000>;
311			interrupts = <32 0>;
312			clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>;
313			status = "disabled";
314		};
315
316		lpi2c2: i2c@40108000 {
317			compatible = "nxp,lpi2c";
318			clock-frequency = <I2C_BITRATE_STANDARD>;
319			#address-cells = <1>;
320			#size-cells = <0>;
321			reg = <0x40108000 0x4000>;
322			interrupts = <33 0>;
323			clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>;
324			status = "disabled";
325		};
326
327		lpi2c3: i2c@4010c000 {
328			compatible = "nxp,lpi2c";
329			clock-frequency = <I2C_BITRATE_STANDARD>;
330			#address-cells = <1>;
331			#size-cells = <0>;
332			reg = <0x4010c000 0x4000>;
333			interrupts = <34 0>;
334			clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>;
335			status = "disabled";
336		};
337
338		lpi2c4: i2c@40110000 {
339			compatible = "nxp,lpi2c";
340			clock-frequency = <I2C_BITRATE_STANDARD>;
341			#address-cells = <1>;
342			#size-cells = <0>;
343			reg = <0x40110000 0x4000>;
344			interrupts = <35 0>;
345			clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>;
346			status = "disabled";
347		};
348
349		lpi2c5: i2c@40c34000 {
350			compatible = "nxp,lpi2c";
351			clock-frequency = <I2C_BITRATE_STANDARD>;
352			#address-cells = <1>;
353			#size-cells = <0>;
354			reg = <0x40c34000 0x4000>;
355			interrupts = <36 0>;
356			clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>;
357			status = "disabled";
358		};
359
360		lpi2c6: i2c@40c38000 {
361			compatible = "nxp,lpi2c";
362			clock-frequency = <I2C_BITRATE_STANDARD>;
363			#address-cells = <1>;
364			#size-cells = <0>;
365			reg = <0x40c38000 0x4000>;
366			interrupts = <37 0>;
367			clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>;
368			status = "disabled";
369		};
370
371		iomuxc: iomuxc@400e8000 {
372			compatible = "nxp,imx-iomuxc";
373			reg = <0x400e8000 0x4000>;
374			status = "okay";
375			pinctrl: pinctrl {
376				status = "okay";
377				compatible = "nxp,mcux-rt11xx-pinctrl";
378			};
379		};
380
381		iomuxc_lpsr: iomuxc_lpsr@40c08000 {
382			compatible = "nxp,mcux-rt-pinctrl";
383			reg = <0x40c08000 0x4000>;
384			status = "disabled";
385		};
386
387		iomuxc_lpsr_gpr: iomuxc_lpsr_gpr@40c08000 {
388			compatible = "nxp,imx-gpr";
389			reg = <0x40c08000 0x4000>;
390			#pinmux-cells = <2>;
391		};
392
393		lcdif: display-controller@40804000 {
394			compatible = "nxp,imx-elcdif";
395			reg = <0x40804000 0x4000>;
396			interrupts = <54 0>;
397			status = "disabled";
398			nxp,pxp = <&pxp>;
399		};
400
401		mipi_dsi: mipi-dsi@4080c000 {
402			compatible = "nxp,imx-mipi-dsi";
403			#address-cells = <1>;
404			#size-cells = <0>;
405			reg = <0x4080c000 0x200>,
406			      <0x4080c200 0x80>,
407			      <0x4080c280 0x80>,
408			      <0x4080c300 0x200>;
409			interrupts = <59 1>;
410			status = "disabled";
411		};
412
413		lpspi1: spi@40114000 {
414			compatible = "nxp,lpspi";
415			reg = <0x40114000 0x4000>;
416			interrupts = <38 3>;
417			status = "disabled";
418			clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>;
419			rx-fifo-size = <16>;
420			tx-fifo-size = <16>;
421			#address-cells = <1>;
422			#size-cells = <0>;
423		};
424
425		lpspi2: spi@40118000 {
426			compatible = "nxp,lpspi";
427			reg = <0x40118000 0x4000>;
428			interrupts = <39 3>;
429			status = "disabled";
430			clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>;
431			rx-fifo-size = <16>;
432			tx-fifo-size = <16>;
433			#address-cells = <1>;
434			#size-cells = <0>;
435		};
436
437		lpspi3: spi@4011c000 {
438			compatible = "nxp,lpspi";
439			reg = <0x4011c000 0x4000>;
440			interrupts = <40 3>;
441			status = "disabled";
442			clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>;
443			rx-fifo-size = <16>;
444			tx-fifo-size = <16>;
445			#address-cells = <1>;
446			#size-cells = <0>;
447		};
448
449		lpspi4: spi@40120000 {
450			compatible = "nxp,lpspi";
451			reg = <0x40120000 0x4000>;
452			interrupts = <41 3>;
453			status = "disabled";
454			clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>;
455			rx-fifo-size = <16>;
456			tx-fifo-size = <16>;
457			#address-cells = <1>;
458			#size-cells = <0>;
459		};
460
461		lpspi5: spi@40c2c000 {
462			compatible = "nxp,lpspi";
463			reg = <0x40c2c000 0x4000>;
464			interrupts = <42 3>;
465			status = "disabled";
466			clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>;
467			rx-fifo-size = <16>;
468			tx-fifo-size = <16>;
469			#address-cells = <1>;
470			#size-cells = <0>;
471		};
472
473		lpspi6: spi@40c30000 {
474			compatible = "nxp,lpspi";
475			reg = <0x40c30000 0x4000>;
476			interrupts = <43 3>;
477			status = "disabled";
478			clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>;
479			rx-fifo-size = <16>;
480			tx-fifo-size = <16>;
481			#address-cells = <1>;
482			#size-cells = <0>;
483		};
484
485		lpuart1: uart@4007c000 {
486			compatible = "nxp,lpuart";
487			reg = <0x4007c000 0x4000>;
488			interrupts = <20 0>;
489			clocks = <&ccm IMX_CCM_LPUART1_CLK 0x7c 24>;
490			status = "disabled";
491		};
492
493		lpuart2: uart@40080000 {
494			compatible = "nxp,lpuart";
495			reg = <0x40080000 0x4000>;
496			interrupts = <21 0>;
497			clocks = <&ccm IMX_CCM_LPUART2_CLK 0x68 28>;
498			status = "disabled";
499		};
500
501		lpuart3: uart@40084000 {
502			compatible = "nxp,lpuart";
503			reg = <0x40084000 0x4000>;
504			interrupts = <22 0>;
505			clocks = <&ccm IMX_CCM_LPUART3_CLK 0x68 12>;
506			status = "disabled";
507		};
508
509		lpuart4: uart@40088000 {
510			compatible = "nxp,lpuart";
511			reg = <0x40088000 0x4000>;
512			interrupts = <23 0>;
513			clocks = <&ccm IMX_CCM_LPUART4_CLK 0x6c 24>;
514			status = "disabled";
515		};
516
517		lpuart5: uart@4008c000 {
518			compatible = "nxp,lpuart";
519			reg = <0x4008c000 0x4000>;
520			interrupts = <24 0>;
521			clocks = <&ccm IMX_CCM_LPUART5_CLK 0x74 2>;
522			status = "disabled";
523		};
524
525		lpuart6: uart@40090000 {
526			compatible = "nxp,lpuart";
527			reg = <0x40090000 0x4000>;
528			interrupts = <25 0>;
529			clocks = <&ccm IMX_CCM_LPUART6_CLK 0x74 6>;
530			status = "disabled";
531		};
532
533		lpuart7: uart@40094000 {
534			compatible = "nxp,lpuart";
535			reg = <0x40094000 0x4000>;
536			interrupts = <26 0>;
537			clocks = <&ccm IMX_CCM_LPUART7_CLK 0x7c 26>;
538			status = "disabled";
539		};
540
541		lpuart8: uart@40098000 {
542			compatible = "nxp,lpuart";
543			reg = <0x40098000 0x4000>;
544			interrupts = <27 0>;
545			clocks = <&ccm IMX_CCM_LPUART8_CLK 0x80 14>;
546			status = "disabled";
547		};
548
549		lpuart9: uart@4009c000 {
550			compatible = "nxp,lpuart";
551			reg = <0x4009c000 0x4000>;
552			interrupts = <28 0>;
553			clocks = <&ccm IMX_CCM_LPUART9_CLK 0x80 14>;
554			status = "disabled";
555		};
556
557		lpuart10: uart@400a0000 {
558			compatible = "nxp,lpuart";
559			reg = <0x400a0000 0x4000>;
560			interrupts = <29 0>;
561			clocks = <&ccm IMX_CCM_LPUART10_CLK 0x80 14>;
562			status = "disabled";
563		};
564
565		lpuart11: uart@40c24000 {
566			compatible = "nxp,lpuart";
567			reg = <0x40c24000 0x4000>;
568			interrupts = <30 0>;
569			clocks = <&ccm IMX_CCM_LPUART11_CLK 0x80 14>;
570			status = "disabled";
571		};
572
573		lpuart12: uart@40c28000 {
574			compatible = "nxp,lpuart";
575			reg = <0x40c28000 0x4000>;
576			interrupts = <31 0>;
577			clocks = <&ccm IMX_CCM_LPUART12_CLK 0x80 14>;
578			status = "disabled";
579		};
580
581		flexpwm1: flexpwm@4018c000 {
582			compatible = "nxp,flexpwm";
583			reg = <0x4018c000 0x4000>;
584			interrupts = <129 0>;
585
586			flexpwm1_pwm0: flexpwm1_pwm0 {
587				compatible = "nxp,imx-pwm";
588				index = <0>;
589				interrupts = <125 0>;
590				#pwm-cells = <3>;
591				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
592				nxp,prescaler = <128>;
593				status = "disabled";
594			};
595
596			flexpwm1_pwm1: flexpwm1_pwm1 {
597				compatible = "nxp,imx-pwm";
598				index = <1>;
599				interrupts = <126 0>;
600				#pwm-cells = <3>;
601				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
602				nxp,prescaler = <128>;
603				status = "disabled";
604			};
605
606			flexpwm1_pwm2: flexpwm1_pwm2 {
607				compatible = "nxp,imx-pwm";
608				index = <2>;
609				interrupts = <127 0>;
610				#pwm-cells = <3>;
611				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
612				nxp,prescaler = <128>;
613				status = "disabled";
614			};
615
616			flexpwm1_pwm3: flexpwm1_pwm3 {
617				compatible = "nxp,imx-pwm";
618				index = <3>;
619				interrupts = <128 0>;
620				#pwm-cells = <3>;
621				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
622				nxp,prescaler = <128>;
623				status = "disabled";
624			};
625		};
626
627		flexpwm2: flexpwm@40190000 {
628			compatible = "nxp,flexpwm";
629			reg = <0x40190000 0x4000>;
630			interrupts =  <181 0>;
631
632			flexpwm2_pwm0: flexpwm2_pwm0 {
633				compatible = "nxp,imx-pwm";
634				index = <0>;
635				interrupts = <177 0>;
636				#pwm-cells = <3>;
637				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
638				nxp,prescaler = <128>;
639				status = "disabled";
640			};
641
642			flexpwm2_pwm1: flexpwm2_pwm1 {
643				compatible = "nxp,imx-pwm";
644				index = <1>;
645				interrupts = <178 0>;
646				#pwm-cells = <3>;
647				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
648				nxp,prescaler = <128>;
649				status = "disabled";
650			};
651
652			flexpwm2_pwm2: flexpwm2_pwm2 {
653				compatible = "nxp,imx-pwm";
654				index = <2>;
655				interrupts = <179 0>;
656				#pwm-cells = <3>;
657				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
658				nxp,prescaler = <128>;
659				status = "disabled";
660			};
661
662			flexpwm2_pwm3: flexpwm2_pwm3 {
663				compatible = "nxp,imx-pwm";
664				index = <3>;
665				interrupts = <180 0>;
666				#pwm-cells = <3>;
667				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
668				nxp,prescaler = <128>;
669				status = "disabled";
670			};
671		};
672
673		flexpwm3: flexpwm@40194000 {
674			compatible = "nxp,flexpwm";
675			reg = <0x40194000 0x4000>;
676			interrupts =  <186 0>;
677
678			flexpwm3_pwm0: flexpwm3_pwm0 {
679				compatible = "nxp,imx-pwm";
680				index = <0>;
681				interrupts = <182 0>;
682				#pwm-cells = <3>;
683				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
684				nxp,prescaler = <128>;
685				status = "disabled";
686			};
687
688			flexpwm3_pwm1: flexpwm3_pwm1 {
689				compatible = "nxp,imx-pwm";
690				index = <1>;
691				interrupts = <183 0>;
692				#pwm-cells = <3>;
693				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
694				nxp,prescaler = <128>;
695				status = "disabled";
696			};
697
698			flexpwm3_pwm2: flexpwm3_pwm2 {
699				compatible = "nxp,imx-pwm";
700				index = <2>;
701				interrupts = <184 0>;
702				#pwm-cells = <3>;
703				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
704				nxp,prescaler = <128>;
705				status = "disabled";
706			};
707
708			flexpwm3_pwm3: flexpwm3_pwm3 {
709				compatible = "nxp,imx-pwm";
710				index = <3>;
711				interrupts = <185 0>;
712				#pwm-cells = <3>;
713				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
714				nxp,prescaler = <128>;
715				status = "disabled";
716			};
717		};
718
719		flexpwm4: flexpwm@40198000 {
720			compatible = "nxp,flexpwm";
721			reg = <0x40198000 0x4000>;
722			interrupts = <191 0>;
723
724			flexpwm4_pwm0: flexpwm4_pwm0 {
725				compatible = "nxp,imx-pwm";
726				index = <0>;
727				interrupts = <187 0>;
728				#pwm-cells = <3>;
729				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
730				nxp,prescaler = <128>;
731				status = "disabled";
732			};
733
734			flexpwm4_pwm1: flexpwm4_pwm1 {
735				compatible = "nxp,imx-pwm";
736				index = <1>;
737				interrupts = <188 0>;
738				#pwm-cells = <3>;
739				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
740				nxp,prescaler = <128>;
741				status = "disabled";
742			};
743
744			flexpwm4_pwm2: flexpwm4_pwm2 {
745				compatible = "nxp,imx-pwm";
746				index = <2>;
747				interrupts = <189 0>;
748				#pwm-cells = <3>;
749				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
750				nxp,prescaler = <128>;
751				status = "disabled";
752			};
753
754			flexpwm4_pwm3: flexpwm4_pwm3 {
755				compatible = "nxp,imx-pwm";
756				index = <3>;
757				interrupts = <190 0>;
758				#pwm-cells = <3>;
759				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
760				nxp,prescaler = <128>;
761				status = "disabled";
762			};
763		};
764
765		flexio1: flexio@400ac000 {
766			compatible = "nxp,flexio";
767			reg = <0x400ac000 0x4000>;
768			interrupts = <110 0>;
769			clocks = <&ccm IMX_CCM_FLEXIO1_CLK 0 0>;
770			status = "disabled";
771		};
772
773		flexio2: flexio@400b0000 {
774			compatible = "nxp,flexio";
775			reg = <0x400b0000 0x4000>;
776			interrupts = <111 0>;
777			clocks = <&ccm IMX_CCM_FLEXIO2_CLK 0 0>;
778			status = "disabled";
779		};
780
781		enet: ethernet@40424000 {
782			compatible = "nxp,enet";
783			reg = <0x40424000 0x628>;
784			clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
785			enet_mac: ethernet {
786				compatible = "nxp,enet-mac";
787				interrupts = <137 0>;
788				interrupt-names = "COMMON";
789				nxp,mdio = <&enet_mdio>;
790				nxp,ptp-clock = <&enet_ptp_clock>;
791				status = "disabled";
792			};
793			enet_mdio: mdio {
794				compatible = "nxp,enet-mdio";
795				status = "disabled";
796				#address-cells = <1>;
797				#size-cells = <0>;
798			};
799			enet_ptp_clock: ptp_clock {
800				compatible = "nxp,enet-ptp-clock";
801				interrupts = <138 0>;
802				status = "disabled";
803				clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
804			};
805		};
806
807		enet1g: ethernet@40420000 {
808			compatible = "nxp,enet1g";
809			reg = <0x40420000 0x628>;
810			clocks = <&ccm IMX_CCM_ENET1G_CLK 0 0>;
811			status = "disabled";
812			enet1g_mac: ethernet {
813				compatible = "nxp,enet-mac";
814				interrupts = <141 0>;
815				interrupt-names = "COMMON";
816				nxp,mdio = <&enet1g_mdio>;
817				nxp,ptp-clock = <&enet1g_ptp_clock>;
818				status = "disabled";
819			};
820			enet1g_mdio: mdio {
821				compatible = "nxp,enet-mdio";
822				status = "disabled";
823				#address-cells = <1>;
824				#size-cells = <0>;
825			};
826			enet1g_ptp_clock: ptp_clock {
827				compatible = "nxp,enet-ptp-clock";
828				interrupts = <142 0>;
829				status = "disabled";
830				clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
831			};
832		};
833
834		caam: caam@40440000 {
835			compatible = "nxp,imx-caam";
836			reg = <0x40440000 0x81000>;
837			interrupts = <69 0>, <70 0>, <71 0>,
838				     <72 0>,  <73 0>,  <74 0>;
839			status = "okay";
840		};
841
842		usb1: usbd@40430000 {
843			compatible = "nxp,ehci";
844			reg = <0x40430000 0x200>;
845			interrupts = <136 1>;
846			interrupt-names = "usb_otg";
847			clocks = <&xtal>;
848			num-bidir-endpoints = <8>;
849			status = "disabled";
850		};
851
852		usb2: usbd@4042c000 {
853			compatible = "nxp,ehci";
854			reg = <0x4042c000 0x200>;
855			interrupts = <135 1>;
856			interrupt-names = "usb_otg";
857			clocks = <&xtal>;
858			num-bidir-endpoints = <8>;
859			status = "disabled";
860		};
861
862		usbphy1: usbphy@40434000 {
863			compatible = "nxp,usbphy";
864			reg = <0x40434000 0x1000>;
865			status = "disabled";
866		};
867
868		usbphy2: usbphy@40438000 {
869			compatible = "nxp,usbphy";
870			reg = <0x40438000 0x1000>;
871			status = "disabled";
872		};
873
874		usdhc1: usdhc@40418000 {
875			compatible = "nxp,imx-usdhc";
876			reg = <0x40418000 0x4000>;
877			status = "disabled";
878			interrupts = <133 0>;
879			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
880			max-current-330 = <1020>;
881			max-current-180 = <1020>;
882			max-bus-freq = <208000000>;
883			min-bus-freq = <400000>;
884		};
885
886		usdhc2: usdhc@4041c000 {
887			compatible = "nxp,imx-usdhc";
888			reg = <0x4041c000 0x4000>;
889			status = "disabled";
890			interrupts = <134 0>;
891			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
892			max-current-330 = <1020>;
893			max-current-180 = <1020>;
894			max-bus-freq = <208000000>;
895			min-bus-freq = <400000>;
896		};
897
898		csi: csi@40800000 {
899			compatible = "nxp,imx-csi";
900			reg = <0x40800000 0x4000>;
901			interrupts = <56 1>;
902			status = "disabled";
903
904			port {
905				csi_ep_in: endpoint {
906					remote-endpoint-label = "mipi_csi2rx_ep_out";
907				};
908			};
909		};
910
911		mipi_csi2rx: mipi_csi2rx@40810000 {
912			compatible = "nxp,mipi-csi2rx";
913			reg = <0x40810000 0x200>;
914			status = "disabled";
915			clocks = <&ccm IMX_CCM_MIPI_CSI2RX_ROOT_CLK 0 0>,
916			<&ccm IMX_CCM_MIPI_CSI2RX_UI_CLK 0 0>,
917			<&ccm IMX_CCM_MIPI_CSI2RX_ESC_CLK 0 0>;
918
919			ports {
920				#address-cells = <1>;
921				#size-cells = <0>;
922
923				port@0 {
924					reg = <0>;
925					mipi_csi2rx_ep_out: endpoint {
926						remote-endpoint-label = "csi_ep_in";
927					};
928				};
929
930				port@1 {
931					reg = <1>;
932				};
933			};
934		};
935
936		flexcan1: can@400c4000 {
937			compatible = "nxp,flexcan-fd", "nxp,flexcan";
938			reg = <0x400c4000 0x1000>;
939			interrupts = <44 0>, <45 0>;
940			interrupt-names = "common", "error";
941			clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
942			clk-source = <0>;
943			status = "disabled";
944		};
945
946		flexcan2: can@400c8000 {
947			compatible = "nxp,flexcan-fd", "nxp,flexcan";
948			reg = <0x400c8000 0x1000>;
949			interrupts = <46 0>, <47 0>;
950			interrupt-names = "common", "error";
951			clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>;
952			clk-source = <0>;
953			status = "disabled";
954		};
955
956		flexcan3: can@40c3c000 {
957			compatible = "nxp,flexcan-fd", "nxp,flexcan";
958			reg = <0x40c3c000 0x1000>;
959			interrupts = <48 0>, <49 0>;
960			interrupt-names = "common", "error";
961			clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>;
962			clk-source = <0>;
963			status = "disabled";
964		};
965
966		wdog1: wdog@40030000 {
967			compatible = "nxp,imx-wdog";
968			reg = <0x40030000 0xA>;
969			status = "disabled";
970			interrupts = <112 0>;
971		};
972
973		ocram: ocram@20200000 {
974			compatible = "zephyr,memory-region", "mmio-sram";
975			zephyr,memory-region = "OCRAM";
976			reg = <0x20200000 DT_SIZE_K(256)>;
977		};
978
979		ocram1: ocram@20240000 {
980			compatible = "zephyr,memory-region", "mmio-sram";
981			zephyr,memory-region = "OCRAM1";
982			reg = <0x20240000 DT_SIZE_K(512)>;
983		};
984
985		ocram2: ocram@202c0000 {
986			compatible = "zephyr,memory-region", "mmio-sram";
987			zephyr,memory-region = "OCRAM2";
988			reg = <0x202c0000 DT_SIZE_K(512)>;
989		};
990
991		lpadc0: adc@40050000 {
992			compatible = "nxp,lpc-lpadc";
993			reg = <0x40050000 0x304>;
994			interrupts = <88 0>;
995			status = "disabled";
996			voltage-ref= <1>;
997			calibration-average = <128>;
998			power-level = <0>;
999			offset-value-a = <10>;
1000			offset-value-b = <10>;
1001			#io-channel-cells = <1>;
1002			clocks = <&ccm IMX_CCM_LPADC1_CLK 0 0>;
1003		};
1004
1005		lpadc1: adc@40054000 {
1006			compatible = "nxp,lpc-lpadc";
1007			reg = <0x40054000 0x304>;
1008			interrupts = <89 0>;
1009			status = "disabled";
1010			clk-divider = <8>;
1011			clk-source = <0>;
1012			voltage-ref= <1>;
1013			calibration-average = <128>;
1014			power-level = <1>;
1015			offset-value-a = <10>;
1016			offset-value-b = <10>;
1017			#io-channel-cells = <1>;
1018			clocks = <&ccm IMX_CCM_LPADC2_CLK 0 0>;
1019		};
1020
1021		acmp1: cmp@401a4000 {
1022			compatible = "nxp,kinetis-acmp";
1023			reg = <0x401a4000 0x4000>;
1024			interrupts = <157 0>;
1025			status = "disabled";
1026		};
1027
1028		acmp2: cmp@401a8000 {
1029			compatible = "nxp,kinetis-acmp";
1030			reg = <0x401a8000 0x4000>;
1031			interrupts = <158 0>;
1032			status = "disabled";
1033		};
1034
1035		acmp3: cmp@401ac000 {
1036			compatible = "nxp,kinetis-acmp";
1037			reg = <0x401ac000 0x4000>;
1038			interrupts = <159 0>;
1039			status = "disabled";
1040		};
1041
1042		acmp4: cmp@401b0000 {
1043			compatible = "nxp,kinetis-acmp";
1044			reg = <0x401b0000 0x4000>;
1045			interrupts = <160 0>;
1046			status = "disabled";
1047		};
1048
1049		anatop: anatop@40c84000 {
1050			compatible = "nxp,imx-anatop";
1051			reg = <0x40c84000 0x4000>;
1052			#clock-cells = <4>;
1053			#pll-clock-cells = <3>;
1054		};
1055
1056		edma0: dma-controller@40070000 {
1057			#dma-cells = <2>;
1058			compatible = "nxp,mcux-edma";
1059			nxp,version = <2>;
1060			dma-channels = <32>;
1061			dma-requests = <208>;
1062			nxp,mem2mem;
1063			nxp,a_on;
1064			reg = <0x40070000 0x4000>,
1065				<0x40074000 0x4000>;
1066			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
1067				status = "disabled";
1068			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
1069				<4 0>, <5 0>, <6 0>, <7 0>,
1070				<8 0>, <9 0>, <10 0>, <11 0>,
1071				<12 0>, <13 0>, <14 0>, <15 0>;
1072			irq-shared-offset = <16>;
1073		};
1074
1075		edma_lpsr0: dma-controller@40c14000 {
1076			#dma-cells = <2>;
1077			compatible = "nxp,mcux-edma";
1078			nxp,version = <2>;
1079			dma-channels = <32>;
1080			dma-requests = <208>;
1081			nxp,mem2mem;
1082			nxp,a_on;
1083			reg = <0x40c14000 0x4000>,
1084				<0x40c18000 0x4000>;
1085			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
1086			status = "disabled";
1087			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
1088				<4 0>, <5 0>, <6 0>, <7 0>,
1089				<8 0>, <9 0>, <10 0>, <11 0>,
1090				<12 0>, <13 0>, <14 0>, <15 0>;
1091			irq-shared-offset = <16>;
1092		};
1093
1094		pxp: pxp@40814000 {
1095			compatible = "nxp,pxp";
1096			reg = <0x40814000 0x4000>;
1097			interrupts = <57 0>;
1098			status = "disabled";
1099			#dma-cells = <0>;
1100		};
1101
1102		iomuxcgpr: iomuxcgpr@400e4000 {
1103			compatible = "nxp,imx-gpr";
1104			reg = <0x400e4000 0x4000>;
1105			#pinmux-cells = <2>;
1106		};
1107
1108		sai1: sai@40404000 {
1109			compatible = "nxp,mcux-i2s";
1110			#address-cells = <1>;
1111			#size-cells = <0>;
1112			#pinmux-cells = <2>;
1113			reg = <0x40404000 0x4000>;
1114			clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>;
1115			/* Source from audio PLL */
1116			clock-mux = <4>;
1117			pre-div = <0>;
1118			podf = <4>;
1119			pll-clocks = <&anatop 0 0 0>,
1120					<&anatop 0 0 30>,
1121					<&anatop 0 0 1>,
1122					<&anatop 0 0 77>,
1123					<&anatop 0 0 100>;
1124			pll-clock-names = "src", "lp", "pd", "num", "den";
1125			pinmuxes = <&iomuxcgpr 0x0 0x100>;
1126			interrupts = <76 0>;
1127			nxp,tx-channel = <1>;
1128			status = "disabled";
1129		};
1130
1131		sai2: sai@40408000 {
1132			compatible = "nxp,mcux-i2s";
1133			#address-cells = <1>;
1134			#size-cells = <0>;
1135			#pinmux-cells = <2>;
1136			reg = <0x40408000 0x4000>;
1137			clocks = <&ccm IMX_CCM_SAI2_CLK 0x2084 4>;
1138			/* Source from audio PLL */
1139			clock-mux = <4>;
1140			pre-div = <0>;
1141			podf = <63>;
1142			pll-clocks = <&anatop 0 0 0>,
1143					<&anatop 0 0 30>,
1144					<&anatop 0 0 1>,
1145					<&anatop 0 0 77>,
1146					<&anatop 0 0 100>;
1147			pll-clock-names = "src", "lp", "pd", "num", "den";
1148			pinmuxes = <&iomuxcgpr 0x4 0x100>;
1149			interrupts = <77 0>;
1150			nxp,tx-channel = <1>;
1151			status = "disabled";
1152		};
1153
1154		sai3: sai@4040c000 {
1155			compatible = "nxp,mcux-i2s";
1156			#address-cells = <1>;
1157			#size-cells = <0>;
1158			#pinmux-cells = <2>;
1159			reg = <0x4040c000 0x4000>;
1160			clocks = <&ccm IMX_CCM_SAI3_CLK 0x2104 4>;
1161			/* Source from audio PLL */
1162			clock-mux = <4>;
1163			pre-div = <0>;
1164			podf = <63>;
1165			pll-clocks = <&anatop 0 0 0>,
1166					<&anatop 0 0 30>,
1167					<&anatop 0 0 1>,
1168					<&anatop 0 0 77>,
1169					<&anatop 0 0 100>;
1170			pll-clock-names = "src", "lp", "pd", "num", "den";
1171			pinmuxes = <&iomuxcgpr 0x8 0x100>;
1172			interrupts = <78 0>, <79 0>;
1173			nxp,tx-channel = <1>;
1174			status = "disabled";
1175		};
1176
1177		sai4: sai@40c40000 {
1178			compatible = "nxp,mcux-i2s";
1179			#address-cells = <1>;
1180			#size-cells = <0>;
1181			#pinmux-cells = <2>;
1182			reg = <0x40c40000 0x4000>;
1183			clocks = <&ccm IMX_CCM_SAI4_CLK 0x2184 6>;
1184			/* Source from audio PLL */
1185			clock-mux = <6>;
1186			pre-div = <0>;
1187			podf = <63>;
1188			pll-clocks = <&anatop 0 0 0>,
1189					<&anatop 0 0 30>,
1190					<&anatop 0 0 1>,
1191					<&anatop 0 0 77>,
1192					<&anatop 0 0 100>;
1193			pll-clock-names = "src", "lp", "pd", "num", "den";
1194			pinmuxes = <&iomuxcgpr 0x8 0x200>;
1195			interrupts = <80 0>, <81 0>;
1196			nxp,tx-channel = <1>;
1197			status = "disabled";
1198		};
1199
1200		src: reset-controller@40c04000 {
1201			compatible = "nxp,imx-src-rev2";
1202			reg = <0x40c04000 0x4000>;
1203			status = "okay";
1204		};
1205
1206
1207		qdec1: qdec@40174000 {
1208			compatible = "nxp,mcux-qdec";
1209			reg = <0x40174000 0x4000>;
1210			interrupts = <165 0>;
1211			status = "disabled";
1212		};
1213
1214		qdec2: qdec@40178000 {
1215			compatible = "nxp,mcux-qdec";
1216			reg = <0x40178000 0x4000>;
1217			interrupts = <166 0>;
1218			status = "disabled";
1219		};
1220
1221		qdec3: qdec@4017c000 {
1222			compatible = "nxp,mcux-qdec";
1223			reg = <0x4017c000 0x4000>;
1224			interrupts = <167 0>;
1225			status = "disabled";
1226		};
1227
1228		qdec4: qdec@40180000 {
1229			compatible = "nxp,mcux-qdec";
1230			reg = <0x40180000 0x4000>;
1231			interrupts = <168 0>;
1232			status = "disabled";
1233		};
1234
1235		xbar1: xbar1@4003c000 {
1236			compatible = "nxp,mcux-xbar";
1237			reg = <0x4003c000 0x4000>;
1238			interrupts = <143 0>, <144 0>;
1239			status = "disabled";
1240		};
1241
1242		xbar2: xbar2@40040000 {
1243			compatible = "nxp,mcux-xbar";
1244			reg = <0x40040000 0x4000>;
1245			status = "disabled";
1246		};
1247
1248		xbar3: xbar3@40044000 {
1249			compatible = "nxp,mcux-xbar";
1250			reg = <0x40044000 0x4000>;
1251			status = "disabled";
1252		};
1253
1254		pit1: pit@400d8000 {
1255			compatible = "nxp,pit";
1256			reg = <0x400d8000 0x4000>;
1257			clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
1258			interrupts = <155 0>;
1259			max-load-value = <0xffffffff>;
1260			status = "disabled";
1261			#address-cells = <1>;
1262			#size-cells = <0>;
1263
1264			pit1_channel0: pit1_channel@0 {
1265				compatible = "nxp,pit-channel";
1266				reg = <0>;
1267				status = "disabled";
1268			};
1269
1270			pit1_channel1: pit1_channel@1 {
1271				compatible = "nxp,pit-channel";
1272				reg = <1>;
1273				status = "disabled";
1274			};
1275
1276			pit1_channel2: pit1_channel@2 {
1277				compatible = "nxp,pit-channel";
1278				reg = <2>;
1279				status = "disabled";
1280			};
1281
1282			pit1_channel3: pit1_channel@3 {
1283				compatible = "nxp,pit-channel";
1284				reg = <3>;
1285				status = "disabled";
1286			};
1287		};
1288
1289		pit2: pit@40cb0000 {
1290			compatible = "nxp,pit";
1291			reg = <0x40cb0000 0x4000>;
1292			clocks = <&ccm IMX_CCM_PIT1_CLK 0x0 0>;
1293			interrupts = <156 0>;
1294			max-load-value = <0xffffffff>;
1295			status = "disabled";
1296			#address-cells = <1>;
1297			#size-cells = <0>;
1298
1299			pit2_channel0: pit2_channel@0 {
1300				compatible = "nxp,pit-channel";
1301				reg = <0>;
1302				status = "disabled";
1303				};
1304			pit2_channel1: pit2_channel@1 {
1305				compatible = "nxp,pit-channel";
1306				reg = <1>;
1307				status = "disabled";
1308				};
1309			pit2_channel2: pit2_channel@2 {
1310				compatible = "nxp,pit-channel";
1311				reg = <2>;
1312				status = "disabled";
1313			};
1314			pit2_channel3: pit2_channel@3 {
1315				compatible = "nxp,pit-channel";
1316				reg = <3>;
1317				status = "disabled";
1318			};
1319		};
1320	};
1321};
1322
1323&nvic {
1324	arm,num-irq-priority-bits = <4>;
1325};
1326
1327&systick {
1328	/*
1329	 * RT11xx relies by default on the GPT Timer for system clock
1330	 * implementation, so the SysTick node should not be enabled.
1331	 */
1332	status = "disabled";
1333};
1334