1/*
2 * Copyright 2024-2025 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/clock/imx_ccm_rev2.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <zephyr/dt-bindings/adc/adc.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12
13/ {
14	aliases {
15		watchdog0 = &rtwdog0;
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,cortex-m33f";
25			reg = <0>;
26
27			#address-cells = <1>;
28			#size-cells = <1>;
29			d-cache-line-size = <32>;
30
31			mpu: mpu@e000ed90 {
32				compatible = "arm,armv8m-mpu";
33				reg = <0xe000ed90 0x40>;
34			};
35		};
36		cpu@1 {
37			device_type = "cpu";
38			compatible = "arm,cortex-m7";
39			reg = <1>;
40
41			#address-cells = <1>;
42			#size-cells = <1>;
43			d-cache-line-size = <32>;
44
45			mpu: mpu@e000ed90 {
46				compatible = "arm,armv7m-mpu";
47				reg = <0xe000ed90 0x40>;
48			};
49		};
50	};
51
52	/* USB PLL */
53	usbclk: usbpll-clock {
54		compatible = "fixed-clock";
55		clock-frequency = <24000000>;
56		#clock-cells = <0>;
57	};
58};
59
60&peripheral {
61	#address-cells = <1>;
62	#size-cells = <1>;
63	/*
64	 * Note that the offsets here are relative to the base address
65	 * defined in either nxp_rt118x_cm33_ns.dtsi, nxp_rt118x_cm33.dtsi
66	 * or nxp_rt118x_cm7.dtsi. The base addresses on cm33 core differ
67	 * between non-secure (0x40000000) and secure modes (0x50000000).
68	 */
69	iomuxc: iomuxc@2A10000 {
70		compatible = "nxp,imx-iomuxc";
71		reg = <0x2A10000 0x4000>;
72		pinctrl: pinctrl {
73			status = "okay";
74			compatible = "nxp,mcux-rt11xx-pinctrl";
75		};
76	};
77
78	iomuxc_aon: iomuxc@43C0000 {
79		compatible = "nxp,mcux-rt-pinctrl";
80		reg = <0x43C0000 0x4000>;
81		status = "okay";
82	};
83
84	ccm: ccm@4450000 {
85		compatible = "nxp,imx-ccm-rev2";
86		reg = <0x4450000 0x4000>;
87		#clock-cells = <3>;
88
89		lpo: lpo32k {
90			compatible = "fixed-clock";
91			clock-frequency = <32000>;
92			#clock-cells = <0>;
93		};
94	};
95
96	lpuart1: uart@4380000 {
97		compatible = "nxp,lpuart";
98		reg = <0x4380000 0x4000>;
99		interrupts = <19 0>;
100		clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x7c 24>;
101		dmas = <&edma3 0 16>, <&edma3 1 17>;
102		dma-names = "tx", "rx";
103		status = "disabled";
104	};
105
106	lpuart2: uart@4390000 {
107		compatible = "nxp,lpuart";
108		reg = <0x4390000 0x4000>;
109		interrupts = <20 0>;
110		clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x68 28>;
111		dmas = <&edma3 2 18>, <&edma3 3 19>;
112		dma-names = "tx", "rx";
113		status = "disabled";
114	};
115
116	lpuart3: uart@2570000 {
117		compatible = "nxp,lpuart";
118		reg = <0x2570000 0x4000>;
119		interrupts = <68 0>;
120		clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x68 12>;
121		dmas = <&edma4 0 17>, <&edma4 1 18>;
122		dma-names = "tx", "rx";
123		status = "disabled";
124	};
125
126	lpuart4: uart@2580000 {
127		compatible = "nxp,lpuart";
128		reg = <0x2580000 0x4000>;
129		interrupts = <69 0>;
130		clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x6c 24>;
131		dmas = <&edma4 2 19>, <&edma4 3 20>;
132		dma-names = "tx", "rx";
133		status = "disabled";
134	};
135
136	lpuart5: uart@2590000 {
137		compatible = "nxp,lpuart";
138		reg = <0x2590000 0x4000>;
139		interrupts = <70 0>;
140		clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 2>;
141		dmas = <&edma4 4 21>, <&edma4 5 22>;
142		dma-names = "tx", "rx";
143		status = "disabled";
144	};
145
146	lpuart6: uart@25A0000 {
147		compatible = "nxp,lpuart";
148		reg = <0x25A0000 0x4000>;
149		interrupts = <71 0>;
150		clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 6>;
151		dmas = <&edma4 6 23>, <&edma4 7 24>;
152		dma-names = "tx", "rx";
153		status = "disabled";
154	};
155
156	lpuart7: uart@4570000 {
157		compatible = "nxp,lpuart";
158		reg = <0x4570000 0x4000>;
159		interrupts = <196 0>;
160		clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x7c 26>;
161		dmas = <&edma3 4 29>, <&edma3 5 30>;
162		dma-names = "tx", "rx";
163		status = "disabled";
164	};
165
166	lpuart8: uart@2DA0000 {
167		compatible = "nxp,lpuart";
168		reg = <0x2DA0000 0x4000>;
169		interrupts = <197 0>;
170		clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x80 14>;
171		dmas = <&edma4 8 178>, <&edma4 9 179>;
172		dma-names = "tx", "rx";
173		status = "disabled";
174	};
175
176	lpuart9: uart@2D70000 {
177		compatible = "nxp,lpuart";
178		reg = <0x2D70000 0x4000>;
179		interrupts = <156 0>;
180		clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>;
181		dmas = <&edma4 10 172>, <&edma4 11 173>;
182		dma-names = "tx", "rx";
183		status = "disabled";
184	};
185
186	lpuart10: uart@2D80000 {
187		compatible = "nxp,lpuart";
188		reg = <0x2D80000 0x4000>;
189		interrupts = <157 0>;
190		clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>;
191		dmas = <&edma4 12 174>, <&edma4 13 175>;
192		dma-names = "tx", "rx";
193		status = "disabled";
194	};
195
196	lpuart11: uart@2D90000 {
197		compatible = "nxp,lpuart";
198		reg = <0x2D90000 0x4000>;
199		interrupts = <158 0>;
200		clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>;
201		dmas = <&edma4 14 176>, <&edma4 15 177>;
202		dma-names = "tx", "rx";
203		status = "disabled";
204	};
205
206	lpuart12: uart@4580000 {
207		compatible = "nxp,lpuart";
208		reg = <0x4580000 0x4000>;
209		interrupts = <159 0>;
210		clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>;
211		dmas = <&edma3 6 31>, <&edma3 7 32>;
212		dma-names = "tx", "rx";
213		status = "disabled";
214	};
215
216	gpio1: gpio@7400000 {
217		compatible = "nxp,imx-rgpio";
218		reg = <0x7400000 0x4000>;
219		interrupts = <10 0>, <11 0>;
220		gpio-controller;
221		#gpio-cells = <2>;
222	};
223
224	gpio2: gpio@3810000 {
225		compatible = "nxp,imx-rgpio";
226		reg = <0x3810000 0x4000>;
227		interrupts = <57 0>, <58 0>;
228		gpio-controller;
229		#gpio-cells = <2>;
230	};
231
232	gpio3: gpio@3820000 {
233		compatible = "nxp,imx-rgpio";
234		reg = <0x3820000 0x4000>;
235		interrupts = <59 0>, <60 0>;
236		gpio-controller;
237		#gpio-cells = <2>;
238	};
239
240	gpio4: gpio@3830000 {
241		compatible = "nxp,imx-rgpio";
242		reg = <0x3830000 0x4000>;
243		interrupts = <232 0>;
244		gpio-controller;
245		#gpio-cells = <2>;
246	};
247
248	gpio5: gpio@3840000 {
249		compatible = "nxp,imx-rgpio";
250		reg = <0x3840000 0x4000>;
251		interrupts = <234 0>;
252		gpio-controller;
253		#gpio-cells = <2>;
254	};
255
256	gpio6: gpio@3850000 {
257		compatible = "nxp,imx-rgpio";
258		reg = <0x3850000 0x4000>;
259		interrupts = <236 0>;
260		gpio-controller;
261		#gpio-cells = <2>;
262	};
263
264	lpi2c1: i2c@4340000 {
265		compatible = "nxp,lpi2c";
266		clock-frequency = <I2C_BITRATE_STANDARD>;
267		#address-cells = <1>;
268		#size-cells = <0>;
269		reg = <0x4340000 0x4000>;
270		interrupts = <13 0>;
271		clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 6>;
272		status = "disabled";
273	};
274
275	lpi2c2: i2c@4350000 {
276		compatible = "nxp,lpi2c";
277		clock-frequency = <I2C_BITRATE_STANDARD>;
278		#address-cells = <1>;
279		#size-cells = <0>;
280		reg = <0x4350000 0x4000>;
281		interrupts = <14 0>;
282		clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 8>;
283		status = "disabled";
284	};
285
286	lpi2c3: i2c@2530000 {
287		compatible = "nxp,lpi2c";
288		clock-frequency = <I2C_BITRATE_STANDARD>;
289		#address-cells = <1>;
290		#size-cells = <0>;
291		reg = <0x2530000 0x4000>;
292		interrupts = <62 0>;
293		clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x70 10>;
294		status = "disabled";
295	};
296
297	lpi2c4: i2c@2540000 {
298		compatible = "nxp,lpi2c";
299		clock-frequency = <I2C_BITRATE_STANDARD>;
300		#address-cells = <1>;
301		#size-cells = <0>;
302		reg = <0x2540000 0x4000>;
303		interrupts = <63 0>;
304		clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x80 24>;
305		status = "disabled";
306	};
307
308	lpi2c5: i2c@2d30000 {
309		compatible = "nxp,lpi2c";
310		clock-frequency = <I2C_BITRATE_STANDARD>;
311		#address-cells = <1>;
312		#size-cells = <0>;
313		reg = <0x2d30000 0x4000>;
314		interrupts = <152 0>;
315		clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>;
316		status = "disabled";
317	};
318
319	lpi2c6: i2c@2d40000 {
320		compatible = "nxp,lpi2c";
321		clock-frequency = <I2C_BITRATE_STANDARD>;
322		#address-cells = <1>;
323		#size-cells = <0>;
324		reg = <0x2d40000 0x4000>;
325		interrupts = <153 0>;
326		clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>;
327		status = "disabled";
328	};
329
330	gpt1: gpt@46c0000 {
331		compatible = "nxp,imx-gpt";
332		reg = <0x46c0000 0x4000>;
333		interrupts = <209 0>;
334		gptfreq = <240000000>;
335		clocks = <&ccm IMX_CCM_GPT1_CLK 0x41 0>;
336		status = "disabled";
337	};
338
339	gpt2: gpt@2ec0000 {
340		compatible = "nxp,imx-gpt";
341		reg = <0x2ec0000 0x4000>;
342		interrupts = <210 0>;
343		gptfreq = <240000000>;
344		clocks = <&ccm IMX_CCM_GPT2_CLK 0x41 0>;
345	};
346
347	acmp1: cmp@2dc0000 {
348		compatible = "nxp,kinetis-acmp";
349		reg = <0x2dc0000 0x4000>;
350		interrupts = <200 0>;
351		status = "disabled";
352	};
353
354	acmp2: cmp@2dd0000 {
355		compatible = "nxp,kinetis-acmp";
356		reg = <0x2dd0000 0x4000>;
357		interrupts = <201 0>;
358		status = "disabled";
359	};
360
361	acmp3: cmp@2de0000 {
362		compatible = "nxp,kinetis-acmp";
363		reg = <0x2de0000 0x4000>;
364		interrupts = <202 0>;
365		status = "disabled";
366	};
367
368	acmp4: cmp@2df0000 {
369		compatible = "nxp,kinetis-acmp";
370		reg = <0x2df0000 0x4000>;
371		interrupts = <203 0>;
372		status = "disabled";
373	};
374
375	lpadc1: adc@2600000 {
376		compatible = "nxp,lpc-lpadc";
377		reg = <0x2600000 0x304>;
378		interrupts = <93 0>;
379		status = "disabled";
380		voltage-ref= <1>;
381		calibration-average = <128>;
382		no-power-level;
383		offset-value-a = <10>;
384		offset-value-b = <10>;
385		#io-channel-cells = <1>;
386		clocks = <&ccm IMX_CCM_LPADC1_CLK 0 0>;
387	};
388
389	lpadc2: adc@2e00000 {
390		compatible = "nxp,lpc-lpadc";
391		reg = <0x2e00000 0x304>;
392		interrupts = <189 0>;
393		status = "disabled";
394		clk-divider = <8>;
395		clk-source = <0>;
396		voltage-ref= <1>;
397		calibration-average = <128>;
398		no-power-level;
399		offset-value-a = <10>;
400		offset-value-b = <10>;
401		#io-channel-cells = <1>;
402		clocks = <&ccm IMX_CCM_LPADC2_CLK 0 0>;
403	};
404
405	qtmr1: qtmr@2690000 {
406		compatible = "nxp,imx-qtmr";
407		reg = <0x2690000 0x4000>;
408		interrupts = <0 0>;
409		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
410		qtmr1_timer0: timer0 {
411			compatible = "nxp,imx-tmr";
412			channel = <0>;
413			status = "disabled";
414		};
415		qtmr1_timer1: timer1 {
416			compatible = "nxp,imx-tmr";
417			channel = <1>;
418			status = "disabled";
419		};
420		qtmr1_timer2: timer2 {
421			compatible = "nxp,imx-tmr";
422			channel = <2>;
423			status = "disabled";
424		};
425		qtmr1_timer3: timer3 {
426			compatible = "nxp,imx-tmr";
427			channel = <3>;
428			status = "disabled";
429		};
430	};
431
432	qtmr2: qtmr@26a0000 {
433		compatible = "nxp,imx-qtmr";
434		reg = <0x26a0000 0x4000>;
435		interrupts = <233 0>;
436		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
437		qtmr2_timer0: timer0 {
438			compatible = "nxp,imx-tmr";
439			channel = <0>;
440			status = "disabled";
441		};
442		qtmr2_timer1: timer1 {
443			compatible = "nxp,imx-tmr";
444			channel = <1>;
445			status = "disabled";
446		};
447		qtmr2_timer2: timer2 {
448			compatible = "nxp,imx-tmr";
449			channel = <2>;
450			status = "disabled";
451		};
452		qtmr2_timer3: timer3 {
453			compatible = "nxp,imx-tmr";
454			channel = <3>;
455			status = "disabled";
456		};
457	};
458
459	qtmr3: qtmr@26b0000 {
460		compatible = "nxp,imx-qtmr";
461		reg = <0x26b0000 0x4000>;
462		interrupts = <164 0>;
463		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
464		qtmr3_timer0: timer0 {
465			compatible = "nxp,imx-tmr";
466			channel = <0>;
467			status = "disabled";
468		};
469		qtmr3_timer1: timer1 {
470			compatible = "nxp,imx-tmr";
471			channel = <1>;
472			status = "disabled";
473		};
474		qtmr3_timer2: timer2 {
475			compatible = "nxp,imx-tmr";
476			channel = <2>;
477			status = "disabled";
478		};
479		qtmr3_timer3: timer3 {
480			compatible = "nxp,imx-tmr";
481			channel = <3>;
482			status = "disabled";
483		};
484	};
485
486	qtmr4: qtmr@26c0000 {
487		compatible = "nxp,imx-qtmr";
488		reg = <0x26c0000 0x4000>;
489		interrupts = <151 0>;
490		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
491		qtmr4_timer0: timer0 {
492			compatible = "nxp,imx-tmr";
493			channel = <0>;
494			status = "disabled";
495		};
496		qtmr4_timer1: timer1 {
497			compatible = "nxp,imx-tmr";
498			channel = <1>;
499			status = "disabled";
500		};
501		qtmr4_timer2: timer2 {
502			compatible = "nxp,imx-tmr";
503			channel = <2>;
504			status = "disabled";
505		};
506		qtmr4_timer3: timer3 {
507			compatible = "nxp,imx-tmr";
508			channel = <3>;
509			status = "disabled";
510		};
511	};
512
513	qtmr5: qtmr@26d0000 {
514		compatible = "nxp,imx-qtmr";
515		reg = <0x26d0000 0x4000>;
516		interrupts = <4 0>;
517		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
518		qtmr5_timer0: timer0 {
519			compatible = "nxp,imx-tmr";
520			channel = <0>;
521			status = "disabled";
522		};
523		qtmr5_timer1: timer1 {
524			compatible = "nxp,imx-tmr";
525			channel = <1>;
526			status = "disabled";
527		};
528		qtmr5_timer2: timer2 {
529			compatible = "nxp,imx-tmr";
530			channel = <2>;
531			status = "disabled";
532		};
533		qtmr5_timer3: timer3 {
534			compatible = "nxp,imx-tmr";
535			channel = <3>;
536			status = "disabled";
537		};
538	};
539
540	qtmr6: qtmr@26e0000 {
541		compatible = "nxp,imx-qtmr";
542		reg = <0x26e0000 0x4000>;
543		interrupts = <5 0>;
544		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
545		qtmr6_timer0: timer0 {
546			compatible = "nxp,imx-tmr";
547			channel = <0>;
548			status = "disabled";
549		};
550		qtmr6_timer1: timer1 {
551			compatible = "nxp,imx-tmr";
552			channel = <1>;
553			status = "disabled";
554		};
555		qtmr6_timer2: timer2 {
556			compatible = "nxp,imx-tmr";
557			channel = <2>;
558			status = "disabled";
559		};
560		qtmr6_timer3: timer3 {
561			compatible = "nxp,imx-tmr";
562			channel = <3>;
563			status = "disabled";
564		};
565	};
566
567	qtmr7: qtmr@26f0000 {
568		compatible = "nxp,imx-qtmr";
569		reg = <0x26f0000 0x4000>;
570		interrupts = <6 0>;
571		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
572		qtmr7_timer0: timer0 {
573			compatible = "nxp,imx-tmr";
574			channel = <0>;
575			status = "disabled";
576		};
577		qtmr7_timer1: timer1 {
578			compatible = "nxp,imx-tmr";
579			channel = <1>;
580			status = "disabled";
581		};
582		qtmr7_timer2: timer2 {
583			compatible = "nxp,imx-tmr";
584			channel = <2>;
585			status = "disabled";
586		};
587		qtmr7_timer3: timer3 {
588			compatible = "nxp,imx-tmr";
589			channel = <3>;
590			status = "disabled";
591		};
592	};
593
594	qtmr8: qtmr@2700000 {
595		compatible = "nxp,imx-qtmr";
596		reg = <0x2700000 0x4000>;
597		interrupts = <7 0>;
598		clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>;
599		qtmr8_timer0: timer0 {
600			compatible = "nxp,imx-tmr";
601			channel = <0>;
602			status = "disabled";
603		};
604		qtmr8_timer1: timer1 {
605			compatible = "nxp,imx-tmr";
606			channel = <1>;
607			status = "disabled";
608		};
609		qtmr8_timer2: timer2 {
610			compatible = "nxp,imx-tmr";
611			channel = <2>;
612			status = "disabled";
613		};
614		qtmr8_timer3: timer3 {
615			compatible = "nxp,imx-tmr";
616			channel = <3>;
617			status = "disabled";
618		};
619	};
620
621	netc: ethernet@60000000 {
622		reg = <0x60000000 0x1000000>;
623		#address-cells = <1>;
624		#size-cells = <1>;
625		ranges;
626
627		enetc_psi0: ethernet@60b00000 {
628			compatible = "nxp,imx-netc-psi";
629			reg = <0x60b00000 0x10000>;
630			mac-index = <0>;
631			si-index = <0>;
632			status = "disabled";
633		};
634
635		enetc_psi1: ethernet@60b40000 {
636			compatible = "nxp,imx-netc-psi";
637			reg = <0x60b40000 0x10000>;
638			mac-index = <1>;
639			si-index = <1>;
640			phy-connection-type = "internal";
641			status = "disabled";
642		};
643
644		emdio: mdio@60ba0000 {
645			compatible = "nxp,imx-netc-emdio";
646			reg = <0x60ba0000 0x1c44>;
647			clocks = <&ccm IMX_CCM_NETC_CLK 0x0 0>;
648			#address-cells = <1>;
649			#size-cells = <0>;
650			status = "disabled";
651		};
652
653		switch: dsa {
654			compatible = "nxp,netc-switch";
655			status = "disabled";
656			#address-cells = <1>;
657			#size-cells = <0>;
658
659			switch_port0: switch_port@0 {
660				reg = <0>;
661				status = "disabled";
662			};
663
664			switch_port1: switch_port@1 {
665				reg = <1>;
666				status = "disabled";
667			};
668
669			switch_port2: switch_port@2 {
670				reg = <2>;
671				status = "disabled";
672			};
673
674			switch_port3: switch_port@3 {
675				reg = <3>;
676				status = "disabled";
677			};
678
679			/* Internal port */
680			switch_port4: switch_port@4 {
681				reg = <4>;
682				ethernet = <&enetc_psi1>;
683				phy-connection-type = "internal";
684				status = "disabled";
685			};
686		};
687	};
688
689	flexcan1: can@43a0000 {
690		compatible = "nxp,flexcan-fd", "nxp,flexcan";
691		reg = <0x43a0000 0x1000>;
692		interrupts = <8 0>, <9 0>;
693		interrupt-names = "common", "error";
694		clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
695		clk-source = <0>;
696		status = "disabled";
697	};
698
699	flexcan2: can@25b0000 {
700		compatible = "nxp,flexcan-fd", "nxp,flexcan";
701		reg = <0x25b0000 0x1000>;
702		interrupts = <51 0>, <52 0>;
703		interrupt-names = "common", "error";
704		clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>;
705		clk-source = <0>;
706		status = "disabled";
707	};
708
709	flexcan3: can@45b0000 {
710		compatible = "nxp,flexcan-fd", "nxp,flexcan";
711		reg = <0x45b0000 0x1000>;
712		interrupts = <191 0>, <192 0>;
713		interrupt-names = "common", "error";
714		clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>;
715		clk-source = <0>;
716		status = "disabled";
717	};
718
719	lptmr1: lptmr@4300000 {
720		compatible = "nxp,lptmr";
721		reg = <0x4300000 0x1000>;
722		interrupts = <18 0>;
723		clock-frequency = <80000000>;
724		prescaler = <1>;
725		clk-source = <0>;
726		resolution = <32>;
727		status = "disabled";
728	};
729
730	lptmr2: lptmr@24d0000 {
731		compatible = "nxp,lptmr";
732		reg = <0x24d0000 0x1000>;
733		interrupts = <67 0>;
734		clock-frequency = <80000000>;
735		prescaler = <1>;
736		clk-source = <0>;
737		resolution = <32>;
738		status = "disabled";
739	};
740
741	lptmr3: lptmr@2cd0000 {
742		compatible = "nxp,lptmr";
743		reg = <0x2cd0000 0x1000>;
744		interrupts = <150 0>;
745		clock-frequency = <80000000>;
746		prescaler = <1>;
747		clk-source = <0>;
748		resolution = <32>;
749		status = "disabled";
750	};
751
752	flexpwm1: flexpwm@2650000 {
753		compatible = "nxp,flexpwm";
754		reg = <0x2650000 0x4000>;
755		interrupts = <23 0>;
756
757		flexpwm1_pwm0: flexpwm1_pwm0 {
758			compatible = "nxp,imx-pwm";
759			index = <0>;
760			interrupts = <24 0>;
761			#pwm-cells = <3>;
762			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
763			nxp,prescaler = <128>;
764			status = "disabled";
765		};
766
767		flexpwm1_pwm1: flexpwm1_pwm1 {
768			compatible = "nxp,imx-pwm";
769			index = <1>;
770			interrupts = <25 0>;
771			#pwm-cells = <3>;
772			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
773			nxp,prescaler = <128>;
774			status = "disabled";
775		};
776
777		flexpwm1_pwm2: flexpwm1_pwm2 {
778			compatible = "nxp,imx-pwm";
779			index = <2>;
780			interrupts = <26 0>;
781			#pwm-cells = <3>;
782			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
783			nxp,prescaler = <128>;
784			status = "disabled";
785		};
786
787		flexpwm1_pwm3: flexpwm1_pwm3 {
788			compatible = "nxp,imx-pwm";
789			index = <3>;
790			interrupts = <27 0>;
791			#pwm-cells = <3>;
792			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
793			nxp,prescaler = <128>;
794			status = "disabled";
795		};
796	};
797
798	flexpwm2: flexpwm@2660000 {
799		compatible = "nxp,flexpwm";
800		reg = <0x2660000 0x4000>;
801		interrupts =  <170 0>;
802
803		flexpwm2_pwm0: flexpwm2_pwm0 {
804			compatible = "nxp,imx-pwm";
805			index = <0>;
806			interrupts = <171 0>;
807			#pwm-cells = <3>;
808			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
809			nxp,prescaler = <128>;
810			status = "disabled";
811		};
812
813		flexpwm2_pwm1: flexpwm2_pwm1 {
814			compatible = "nxp,imx-pwm";
815			index = <1>;
816			interrupts = <172 0>;
817			#pwm-cells = <3>;
818			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
819			nxp,prescaler = <128>;
820			status = "disabled";
821		};
822
823		flexpwm2_pwm2: flexpwm2_pwm2 {
824			compatible = "nxp,imx-pwm";
825			index = <2>;
826			interrupts = <173 0>;
827			#pwm-cells = <3>;
828			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
829			nxp,prescaler = <128>;
830			status = "disabled";
831		};
832
833		flexpwm2_pwm3: flexpwm2_pwm3 {
834			compatible = "nxp,imx-pwm";
835			index = <3>;
836			interrupts = <174 0>;
837			#pwm-cells = <3>;
838			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
839			nxp,prescaler = <128>;
840			status = "disabled";
841		};
842	};
843
844	flexpwm3: flexpwm@2670000 {
845		compatible = "nxp,flexpwm";
846		reg = <0x2670000 0x4000>;
847		interrupts =  <175 0>;
848
849		flexpwm3_pwm0: flexpwm3_pwm0 {
850			compatible = "nxp,imx-pwm";
851			index = <0>;
852			interrupts = <176 0>;
853			#pwm-cells = <3>;
854			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
855			nxp,prescaler = <128>;
856			status = "disabled";
857		};
858
859		flexpwm3_pwm1: flexpwm3_pwm1 {
860			compatible = "nxp,imx-pwm";
861			index = <1>;
862			interrupts = <177 0>;
863			#pwm-cells = <3>;
864			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
865			nxp,prescaler = <128>;
866			status = "disabled";
867		};
868
869		flexpwm3_pwm2: flexpwm3_pwm2 {
870			compatible = "nxp,imx-pwm";
871			index = <2>;
872			interrupts = <178 0>;
873			#pwm-cells = <3>;
874			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
875			nxp,prescaler = <128>;
876			status = "disabled";
877		};
878
879		flexpwm3_pwm3: flexpwm3_pwm3 {
880			compatible = "nxp,imx-pwm";
881			index = <3>;
882			interrupts = <179 0>;
883			#pwm-cells = <3>;
884			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
885			nxp,prescaler = <128>;
886			status = "disabled";
887		};
888	};
889
890	flexpwm4: flexpwm@2680000 {
891		compatible = "nxp,flexpwm";
892		reg = <0x2680000 0x4000>;
893		interrupts = <180 0>;
894
895		flexpwm4_pwm0: flexpwm4_pwm0 {
896			compatible = "nxp,imx-pwm";
897			index = <0>;
898			interrupts = <181 0>;
899			#pwm-cells = <3>;
900			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
901			nxp,prescaler = <128>;
902			status = "disabled";
903		};
904
905		flexpwm4_pwm1: flexpwm4_pwm1 {
906			compatible = "nxp,imx-pwm";
907			index = <1>;
908			interrupts = <182 0>;
909			#pwm-cells = <3>;
910			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
911			nxp,prescaler = <128>;
912			status = "disabled";
913		};
914
915		flexpwm4_pwm2: flexpwm4_pwm2 {
916			compatible = "nxp,imx-pwm";
917			index = <2>;
918			interrupts = <183 0>;
919			#pwm-cells = <3>;
920			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
921			nxp,prescaler = <128>;
922			status = "disabled";
923		};
924
925		flexpwm4_pwm3: flexpwm4_pwm3 {
926			compatible = "nxp,imx-pwm";
927			index = <3>;
928			interrupts = <184 0>;
929			#pwm-cells = <3>;
930			clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
931			nxp,prescaler = <128>;
932			status = "disabled";
933		};
934	};
935
936	tpm1: pwm@4310000 {
937		compatible = "nxp,kinetis-tpm";
938		reg = <0x4310000 0x88>;
939		interrupts = <36 0>;
940		clocks = <&ccm IMX_CCM_TPM1_CLK 0x3b 0>;
941		prescaler = <16>;
942		status = "disabled";
943		#pwm-cells = <3>;
944	};
945
946	tpm2: pwm@4320000 {
947		compatible = "nxp,kinetis-tpm";
948		reg = <0x4320000 0x88>;
949		interrupts = <37 0>;
950		clocks = <&ccm IMX_CCM_TPM2_CLK 0x3c 0>;
951		prescaler = <16>;
952		status = "disabled";
953		#pwm-cells = <3>;
954	};
955
956	tpm3: pwm@24E0000 {
957		compatible = "nxp,kinetis-tpm";
958		reg = <0x24E0000 0x88>;
959		interrupts = <75 0>;
960		clocks = <&ccm IMX_CCM_TPM3_CLK 0x3d 0>;
961		prescaler = <16>;
962		status = "disabled";
963		#pwm-cells = <3>;
964	};
965
966	tpm4: pwm@24F0000 {
967		compatible = "nxp,kinetis-tpm";
968		reg = <0x24F0000 0x88>;
969		interrupts = <76 0>;
970		clocks = <&ccm IMX_CCM_TPM4_CLK 0x3e 0>;
971		prescaler = <16>;
972		status = "disabled";
973		#pwm-cells = <3>;
974	};
975
976	tpm5: pwm@2500000 {
977		compatible = "nxp,kinetis-tpm";
978		reg = <0x2500000 0x88>;
979		interrupts = <77 0>;
980		clocks = <&ccm IMX_CCM_TPM5_CLK 0x3f 0>;
981		prescaler = <16>;
982		status = "disabled";
983		#pwm-cells = <3>;
984	};
985
986	tpm6: pwm@42510000 {
987		compatible = "nxp,kinetis-tpm";
988		reg = <0x42510000 0x88>;
989		interrupts = <78 0>;
990		clocks = <&ccm IMX_CCM_TPM6_CLK 0x40 0>;
991		prescaler = <16>;
992		status = "disabled";
993		#pwm-cells = <3>;
994	};
995
996	i3c1: i3c@4330000 {
997		compatible = "nxp,mcux-i3c";
998		reg = <0x4330000 0x1000>;
999		interrupts = <12 0>;
1000		clocks = <&ccm IMX_CCM_I3C1_CLK 0x67 0>;
1001		clk-divider = <2>;
1002		clk-divider-slow = <1>;
1003		clk-divider-tc = <1>;
1004		status = "disabled";
1005		#address-cells = <3>;
1006		#size-cells = <0>;
1007	};
1008
1009	i3c2: i3c@2520000 {
1010		compatible = "nxp,mcux-i3c";
1011		reg = <0x2520000 0x1000>;
1012		interrupts = <61 0>;
1013		clocks = <&ccm IMX_CCM_I3C2_CLK 0x68 0>;
1014		clk-divider = <2>;
1015		clk-divider-slow = <1>;
1016		clk-divider-tc = <1>;
1017		status = "disabled";
1018		#address-cells = <3>;
1019		#size-cells = <0>;
1020	};
1021
1022	usdhc1: usdhc@2850000 {
1023		compatible = "nxp,imx-usdhc";
1024		reg = <0x2850000 0x4000>;
1025		status = "disabled";
1026		interrupts = <86 0>;
1027		clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
1028		max-current-330 = <1020>;
1029		max-current-180 = <1020>;
1030		max-bus-freq = <208000000>;
1031		min-bus-freq = <400000>;
1032	};
1033
1034	usdhc2: usdhc@2860000 {
1035		compatible = "nxp,imx-usdhc";
1036		reg = <0x2860000 0x4000>;
1037		status = "disabled";
1038		interrupts = <87 0>;
1039		clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
1040		max-current-330 = <1020>;
1041		max-current-180 = <1020>;
1042		max-bus-freq = <208000000>;
1043		min-bus-freq = <400000>;
1044	};
1045
1046	edma3: dma-controller@4000000 {
1047		#dma-cells = <2>;
1048		compatible = "nxp,mcux-edma";
1049		nxp,version = <4>;
1050		reg = <0x4000000 0x210000>;
1051		dma-channels = <32>;
1052		dma-requests = <39>;
1053		no-error-irq;
1054		interrupts = <95 0>, <96 0>, <97 0>,
1055			<98 0>, <99 0>, <100 0>, <101 0>,
1056			<102 0>, <103 0>, <104 0>, <105 0>,
1057			<106 0>, <107 0>, <108 0>, <109 0>,
1058			<110 0>, <111 0>, <112 0>, <113 0>,
1059			<114 0>, <115 0>, <116 0>, <117 0>,
1060			<118 0>, <119 0>, <120 0>, <121 0>,
1061			<122 0>, <123 0>, <124 0>, <125 0>,
1062			<126 0>, <94 0>;
1063		status = "disabled";
1064	};
1065
1066	edma4: dma-controller@2000000 {
1067		#dma-cells = <2>;
1068		compatible = "nxp,mcux-edma";
1069		nxp,version = <4>;
1070		dma-channels = <64>;
1071		dma-requests = <222>;
1072		reg = <0x2000000 0x4000>;
1073		no-error-irq;
1074		interrupts = <128 0>, <129 0>, <130 0>,
1075			<131 0>, <132 0>, <133 0>, <134 0>,
1076			<135 0>, <136 0>, <137 0>, <138 0>,
1077			<139 0>, <140 0>, <141 0>, <142 0>,
1078			<143 0>, <127 0>;
1079		channels-shared-irq-mask = <0x00000003 0x00000003
1080			 0x0000000C 0x0000000C 0x00000030 0x00000030
1081			 0x000000C0 0x000000C0 0x00000300 0x00000300
1082			 0x00000C00 0x00000C00 0x00003000 0x00003000
1083			 0x0000C000 0x0000C000 0x00030000 0x00030000
1084			 0x000C0000 0x000C0000 0x00300000 0x00300000
1085			 0x00C00000 0x00C00000 0x03000000 0x03000000
1086			 0x0C000000 0x0C000000 0x30000000 0x30000000
1087			 0xC0000000 0xC0000000>;
1088		status = "disabled";
1089	};
1090
1091	lpspi1: spi@4360000 {
1092		compatible = "nxp,lpspi";
1093		reg = <0x4360000 0x4000>;
1094		interrupts = <16 3>;
1095		status = "disabled";
1096		clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 0>;
1097		tx-fifo-size = <16>;
1098		rx-fifo-size = <16>;
1099		#address-cells = <1>;
1100		#size-cells = <0>;
1101	};
1102
1103	lpspi2: spi@4370000 {
1104		compatible = "nxp,lpspi";
1105		reg = <0x4370000 0x4000>;
1106		interrupts = <17 3>;
1107		status = "disabled";
1108		clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 2>;
1109		tx-fifo-size = <16>;
1110		rx-fifo-size = <16>;
1111		#address-cells = <1>;
1112		#size-cells = <0>;
1113	};
1114
1115	lpspi3: spi@2550000 {
1116		compatible = "nxp,lpspi";
1117		reg = <0x2550000 0x4000>;
1118		interrupts = <65 3>;
1119		status = "disabled";
1120		clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 4>;
1121		tx-fifo-size = <16>;
1122		rx-fifo-size = <16>;
1123		#address-cells = <1>;
1124		#size-cells = <0>;
1125	};
1126
1127	lpspi4: spi@2560000 {
1128		compatible = "nxp,lpspi";
1129		reg = <0x2560000 0x4000>;
1130		interrupts = <66 3>;
1131		status = "disabled";
1132		clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 6>;
1133		tx-fifo-size = <16>;
1134		rx-fifo-size = <16>;
1135		#address-cells = <1>;
1136		#size-cells = <0>;
1137	};
1138
1139	lpspi5: spi@2d50000 {
1140		compatible = "nxp,lpspi";
1141		reg = <0x2d50000 0x4000>;
1142		interrupts = <194 3>;
1143		status = "disabled";
1144		clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>;
1145		tx-fifo-size = <16>;
1146		rx-fifo-size = <16>;
1147		#address-cells = <1>;
1148		#size-cells = <0>;
1149	};
1150
1151	lpspi6: spi@2d60000 {
1152		compatible = "nxp,lpspi";
1153		reg = <0x2d60000 0x4000>;
1154		interrupts = <195 3>;
1155		status = "disabled";
1156		clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>;
1157		tx-fifo-size = <16>;
1158		rx-fifo-size = <16>;
1159		#address-cells = <1>;
1160		#size-cells = <0>;
1161	};
1162
1163	rtwdog0: wdog@42d0000 {
1164		compatible = "nxp,rtwdog";
1165		reg = <0x42d0000 0x10>;
1166		status = "okay";
1167		interrupts = <38 0>;
1168		clocks = <&lpo>;
1169		clk-source = <1>;
1170		clk-divider = <1>;
1171	};
1172
1173	rtwdog1: wdog@42e0000 {
1174		compatible = "nxp,rtwdog";
1175		reg = <0x42e0000 0x10>;
1176		status = "disabled";
1177		interrupts = <39 0>;
1178		clocks = <&lpo>;
1179		clk-source = <1>;
1180		clk-divider = <1>;
1181	};
1182
1183	rtwdog2: wdog@2490000 {
1184		compatible = "nxp,rtwdog";
1185		reg = <0x2490000 0x10>;
1186		status = "disabled";
1187		interrupts = <79 0>;
1188		clocks = <&lpo>;
1189		clk-source = <1>;
1190		clk-divider = <1>;
1191	};
1192
1193	rtwdog3: wdog@24a0000 {
1194		compatible = "nxp,rtwdog";
1195		reg = <0x24a0000 0x10>;
1196		status = "disabled";
1197		interrupts = <80 0>;
1198		clocks = <&lpo>;
1199		clk-source = <1>;
1200		clk-divider = <1>;
1201	};
1202
1203	rtwdog4: wdog@24b0000 {
1204		compatible = "nxp,rtwdog";
1205		reg = <0x24b0000 0x10>;
1206		status = "disabled";
1207		interrupts = <81 0>;
1208		clocks = <&lpo>;
1209		clk-source = <1>;
1210		clk-divider = <1>;
1211	};
1212
1213	usb1: usbd@2c80000 {
1214		compatible = "nxp,ehci";
1215		reg = <0x2c80000 0x1000>;
1216		interrupts = <215 0>;
1217		interrupt-names = "usb_otg";
1218		clocks = <&usbclk>;
1219		num-bidir-endpoints = <8>;
1220		status = "disabled";
1221	};
1222
1223	usb2: usbd@2c90000 {
1224		compatible = "nxp,ehci";
1225		reg = <0x2c90000 0x1000>;
1226		interrupts = <214 0>;
1227		interrupt-names = "usb_otg";
1228		clocks = <&usbclk>;
1229		num-bidir-endpoints = <8>;
1230		status = "disabled";
1231	};
1232
1233	usbphy1: usbphy@2ca0000 {
1234		compatible = "nxp,usbphy";
1235		reg = <0x2ca0000 0x1000>;
1236		status = "disabled";
1237	};
1238
1239	usbphy2: usbphy@2cb0000 {
1240		compatible = "nxp,usbphy";
1241		reg = <0x2cb0000 0x1000>;
1242		status = "disabled";
1243	};
1244};
1245
1246&flexspi {
1247	compatible = "nxp,imx-flexspi";
1248	interrupts = <55 0>;
1249	#address-cells = <1>;
1250	#size-cells = <0>;
1251	status = "disabled";
1252	clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
1253};
1254
1255&flexspi2 {
1256	compatible = "nxp,imx-flexspi";
1257	interrupts = <56 0>;
1258	#address-cells = <1>;
1259	#size-cells = <0>;
1260	status = "disabled";
1261	clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0>;
1262};
1263
1264&memory {
1265	#address-cells = <1>;
1266	#size-cells = <1>;
1267	ocram1: ocram@0 {
1268		compatible = "zephyr,memory-region", "mmio-sram";
1269		zephyr,memory-region = "OCRAM1";
1270		/* OCRAM1 first 16K access is blocked by TRDC */
1271		reg = <0x0 DT_SIZE_K(496)>;
1272	};
1273
1274	ocram2: ocram@7c000 {
1275		compatible = "zephyr,memory-region", "mmio-sram";
1276		zephyr,memory-region = "OCRAM2";
1277		reg = <0x7c000 DT_SIZE_K(256)>;
1278	};
1279};
1280