1/*
2 * Copyright (c) 2019 Vestas Wind Systems A/S
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <nxp/nxp_ke1xf.dtsi>
9
10/ {
11	/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
12	 * contiguous block in the memory map, however misaligned accesses
13	 * across the 0x2000_0000 boundary are not supported in the Arm
14	 * Cortex-M4 architecture. For clarity and to avoid the temptation for
15	 * someone to extend sram0 without solving this issue, we define two
16	 * separate memory nodes here and only use the upper one for now. A
17	 * potential solution has been proposed in binutils:
18	 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
19	 */
20	sram_l: memory@1fffc000 {
21		compatible = "zephyr,memory-region", "mmio-sram";
22		reg = <0x1fffc000 DT_SIZE_K(16)>;
23		zephyr,memory-region = "SRAML";
24	};
25
26	sram0: memory@20000000 {
27		compatible = "mmio-sram";
28		reg = <0x20000000 DT_SIZE_K(16)>;
29	};
30};
31
32&ftfe {
33	flash0: flash@0 {
34		compatible = "soc-nv-flash";
35		reg = <0 DT_SIZE_K(256)>;
36		erase-block-size = <DT_SIZE_K(4)>;
37		write-block-size = <8>;
38	};
39};
40