1/* 2 * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <zephyr/dt-bindings/gpio/gpio.h> 9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h> 10#include "cyw20829.dtsi" 11 12/ { 13 soc { 14 15 pinctrl: pinctrl@40400000 { 16 /* scb_i2c_scl */ 17 /omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl { 18 pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_3)>; 19 }; 20 /omit-if-no-ref/ p1_2_scb2_i2c_scl: p1_2_scb2_i2c_scl { 21 pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_7)>; 22 }; 23 /omit-if-no-ref/ p3_2_scb2_i2c_scl: p3_2_scb2_i2c_scl { 24 pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_7)>; 25 }; 26 /omit-if-no-ref/ p4_0_scb0_i2c_scl: p4_0_scb0_i2c_scl { 27 pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_3)>; 28 }; 29 /omit-if-no-ref/ p5_0_scb2_i2c_scl: p5_0_scb2_i2c_scl { 30 pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>; 31 }; 32 33 /* scb_i2c_sda */ 34 /omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda { 35 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_3)>; 36 }; 37 /omit-if-no-ref/ p1_3_scb2_i2c_sda: p1_3_scb2_i2c_sda { 38 pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_7)>; 39 }; 40 /omit-if-no-ref/ p3_3_scb2_i2c_sda: p3_3_scb2_i2c_sda { 41 pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_7)>; 42 }; 43 /omit-if-no-ref/ p4_1_scb0_i2c_sda: p4_1_scb0_i2c_sda { 44 pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_3)>; 45 }; 46 /omit-if-no-ref/ p5_1_scb2_i2c_sda: p5_1_scb2_i2c_sda { 47 pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>; 48 }; 49 50 /* scb_spi_m_clk */ 51 /omit-if-no-ref/ p0_4_scb0_spi_m_clk: p0_4_scb0_spi_m_clk { 52 pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>; 53 }; 54 /omit-if-no-ref/ p1_1_scb1_spi_m_clk: p1_1_scb1_spi_m_clk { 55 pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>; 56 }; 57 /omit-if-no-ref/ p3_1_scb1_spi_m_clk: p3_1_scb1_spi_m_clk { 58 pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>; 59 }; 60 61 /* scb_spi_m_miso */ 62 /omit-if-no-ref/ p0_3_scb0_spi_m_miso: p0_3_scb0_spi_m_miso { 63 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_6)>; 64 }; 65 /omit-if-no-ref/ p1_3_scb1_spi_m_miso: p1_3_scb1_spi_m_miso { 66 pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>; 67 }; 68 /omit-if-no-ref/ p3_3_scb1_spi_m_miso: p3_3_scb1_spi_m_miso { 69 pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>; 70 }; 71 /omit-if-no-ref/ p4_1_scb0_spi_m_miso: p4_1_scb0_spi_m_miso { 72 pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>; 73 }; 74 75 /* scb_spi_m_mosi */ 76 /omit-if-no-ref/ p0_2_scb0_spi_m_mosi: p0_2_scb0_spi_m_mosi { 77 pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_6)>; 78 }; 79 /omit-if-no-ref/ p1_2_scb1_spi_m_mosi: p1_2_scb1_spi_m_mosi { 80 pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>; 81 }; 82 /omit-if-no-ref/ p3_2_scb1_spi_m_mosi: p3_2_scb1_spi_m_mosi { 83 pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>; 84 }; 85 /omit-if-no-ref/ p4_0_scb0_spi_m_mosi: p4_0_scb0_spi_m_mosi { 86 pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>; 87 }; 88 89 /* scb_spi_m_select0 */ 90 /omit-if-no-ref/ p1_0_scb1_spi_m_select0: p1_0_scb1_spi_m_select0 { 91 pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>; 92 }; 93 /omit-if-no-ref/ p3_0_scb1_spi_m_select0: p3_0_scb1_spi_m_select0 { 94 pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_8)>; 95 }; 96 /omit-if-no-ref/ p5_0_scb1_spi_m_select0: p5_0_scb1_spi_m_select0 { 97 pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>; 98 }; 99 /omit-if-no-ref/ p5_1_scb0_spi_m_select0: p5_1_scb0_spi_m_select0 { 100 pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>; 101 }; 102 103 /* scb_spi_m_select1 */ 104 /omit-if-no-ref/ p0_0_scb0_spi_m_select1: p0_0_scb0_spi_m_select1 { 105 pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_DS_6)>; 106 }; 107 /omit-if-no-ref/ p0_5_scb1_spi_m_select1: p0_5_scb1_spi_m_select1 { 108 pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>; 109 }; 110 /omit-if-no-ref/ p3_6_scb1_spi_m_select1: p3_6_scb1_spi_m_select1 { 111 pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_8)>; 112 }; 113 114 /* scb_spi_m_select2 */ 115 /omit-if-no-ref/ p0_1_scb0_spi_m_select2: p0_1_scb0_spi_m_select2 { 116 pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_DS_6)>; 117 }; 118 /omit-if-no-ref/ p0_4_scb1_spi_m_select2: p0_4_scb1_spi_m_select2 { 119 pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>; 120 }; 121 /omit-if-no-ref/ p3_5_scb1_spi_m_select2: p3_5_scb1_spi_m_select2 { 122 pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_8)>; 123 }; 124 125 /* scb_spi_m_select3 */ 126 /omit-if-no-ref/ p0_3_scb1_spi_m_select3: p0_3_scb1_spi_m_select3 { 127 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>; 128 }; 129 /omit-if-no-ref/ p3_4_scb1_spi_m_select3: p3_4_scb1_spi_m_select3 { 130 pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_8)>; 131 }; 132 133 /* scb_spi_s_clk */ 134 /omit-if-no-ref/ p0_4_scb0_spi_s_clk: p0_4_scb0_spi_s_clk { 135 pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>; 136 }; 137 /omit-if-no-ref/ p1_1_scb1_spi_s_clk: p1_1_scb1_spi_s_clk { 138 pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>; 139 }; 140 /omit-if-no-ref/ p3_1_scb1_spi_s_clk: p3_1_scb1_spi_s_clk { 141 pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>; 142 }; 143 144 /* scb_spi_s_miso */ 145 /omit-if-no-ref/ p0_3_scb0_spi_s_miso: p0_3_scb0_spi_s_miso { 146 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_6)>; 147 }; 148 /omit-if-no-ref/ p1_3_scb1_spi_s_miso: p1_3_scb1_spi_s_miso { 149 pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>; 150 }; 151 /omit-if-no-ref/ p3_3_scb1_spi_s_miso: p3_3_scb1_spi_s_miso { 152 pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>; 153 }; 154 /omit-if-no-ref/ p4_1_scb0_spi_s_miso: p4_1_scb0_spi_s_miso { 155 pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>; 156 }; 157 158 /* scb_spi_s_mosi */ 159 /omit-if-no-ref/ p0_2_scb0_spi_s_mosi: p0_2_scb0_spi_s_mosi { 160 pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_6)>; 161 }; 162 /omit-if-no-ref/ p1_2_scb1_spi_s_mosi: p1_2_scb1_spi_s_mosi { 163 pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>; 164 }; 165 /omit-if-no-ref/ p3_2_scb1_spi_s_mosi: p3_2_scb1_spi_s_mosi { 166 pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>; 167 }; 168 /omit-if-no-ref/ p4_0_scb0_spi_s_mosi: p4_0_scb0_spi_s_mosi { 169 pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>; 170 }; 171 172 /* scb_spi_s_select0 */ 173 /omit-if-no-ref/ p1_0_scb1_spi_s_select0: p1_0_scb1_spi_s_select0 { 174 pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>; 175 }; 176 /omit-if-no-ref/ p3_0_scb1_spi_s_select0: p3_0_scb1_spi_s_select0 { 177 pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_8)>; 178 }; 179 /omit-if-no-ref/ p5_0_scb1_spi_s_select0: p5_0_scb1_spi_s_select0 { 180 pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>; 181 }; 182 /omit-if-no-ref/ p5_1_scb0_spi_s_select0: p5_1_scb0_spi_s_select0 { 183 pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>; 184 }; 185 186 /* scb_spi_s_select1 */ 187 /omit-if-no-ref/ p0_0_scb0_spi_s_select1: p0_0_scb0_spi_s_select1 { 188 pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_DS_6)>; 189 }; 190 /omit-if-no-ref/ p0_5_scb1_spi_s_select1: p0_5_scb1_spi_s_select1 { 191 pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>; 192 }; 193 /omit-if-no-ref/ p3_6_scb1_spi_s_select1: p3_6_scb1_spi_s_select1 { 194 pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_8)>; 195 }; 196 197 /* scb_spi_s_select2 */ 198 /omit-if-no-ref/ p0_1_scb0_spi_s_select2: p0_1_scb0_spi_s_select2 { 199 pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_DS_6)>; 200 }; 201 /omit-if-no-ref/ p0_4_scb1_spi_s_select2: p0_4_scb1_spi_s_select2 { 202 pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>; 203 }; 204 /omit-if-no-ref/ p3_5_scb1_spi_s_select2: p3_5_scb1_spi_s_select2 { 205 pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_8)>; 206 }; 207 208 /* scb_spi_s_select3 */ 209 /omit-if-no-ref/ p0_3_scb1_spi_s_select3: p0_3_scb1_spi_s_select3 { 210 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>; 211 }; 212 /omit-if-no-ref/ p3_4_scb1_spi_s_select3: p3_4_scb1_spi_s_select3 { 213 pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_8)>; 214 }; 215 216 /* scb_uart_cts */ 217 /omit-if-no-ref/ p1_0_scb1_uart_cts: p1_0_scb1_uart_cts { 218 pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>; 219 }; 220 /omit-if-no-ref/ p3_0_scb2_uart_cts: p3_0_scb2_uart_cts { 221 pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>; 222 }; 223 /omit-if-no-ref/ p4_0_scb2_uart_cts: p4_0_scb2_uart_cts { 224 pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>; 225 }; 226 /omit-if-no-ref/ p5_0_scb2_uart_cts: p5_0_scb2_uart_cts { 227 pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>; 228 }; 229 230 /* scb_uart_rts */ 231 /omit-if-no-ref/ p1_1_scb1_uart_rts: p1_1_scb1_uart_rts { 232 pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>; 233 }; 234 /omit-if-no-ref/ p3_1_scb2_uart_rts: p3_1_scb2_uart_rts { 235 pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>; 236 }; 237 238 /* scb_uart_rx */ 239 /omit-if-no-ref/ p1_2_scb1_uart_rx: p1_2_scb1_uart_rx { 240 pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>; 241 }; 242 /omit-if-no-ref/ p3_2_scb2_uart_rx: p3_2_scb2_uart_rx { 243 pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>; 244 }; 245 246 /* scb_uart_tx */ 247 /omit-if-no-ref/ p1_3_scb1_uart_tx: p1_3_scb1_uart_tx { 248 pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>; 249 }; 250 /omit-if-no-ref/ p3_3_scb2_uart_tx: p3_3_scb2_uart_tx { 251 pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>; 252 }; 253 254 /* PWM group 0 */ 255 /omit-if-no-ref/ p0_1_pwm0_1: p0_1_pwm0_1 { 256 pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_0)>; 257 }; 258 259 /omit-if-no-ref/ p0_3_pwm0_0: p0_3_pwm0_0 { 260 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_0)>; 261 }; 262 263 /omit-if-no-ref/ p0_5_pwm0_1: p0_5_pwm0_1 { 264 pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_0)>; 265 }; 266 267 /omit-if-no-ref/ p1_1_pwm0_0: p1_1_pwm0_0 { 268 pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_0)>; 269 }; 270 271 /omit-if-no-ref/ p1_3_pwm0_1: p1_3_pwm0_1 { 272 pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_0)>; 273 }; 274 275 /omit-if-no-ref/ p1_5_pwm0_0: p1_5_pwm0_0 { 276 pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_0)>; 277 }; 278 279 /omit-if-no-ref/ p3_0_pwm0_0: p3_0_pwm0_0 { 280 pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_0)>; 281 }; 282 283 /omit-if-no-ref/ p3_2_pwm0_1: p3_2_pwm0_1 { 284 pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_0)>; 285 }; 286 287 /omit-if-no-ref/ p3_4_pwm0_0: p3_4_pwm0_0 { 288 pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_0)>; 289 }; 290 291 /omit-if-no-ref/ p3_6_pwm0_1: p3_6_pwm0_1 { 292 pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_0)>; 293 }; 294 295 /omit-if-no-ref/ p4_1_pwm0_0: p4_1_pwm0_0 { 296 pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_0)>; 297 }; 298 299 /omit-if-no-ref/ p5_0_pwm0_0: p5_0_pwm0_0 { 300 pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_0)>; 301 }; 302 303 /omit-if-no-ref/ p5_2_pwm0_1: p5_2_pwm0_1 { 304 pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_0)>; 305 }; 306 307 /* PWM group 1 */ 308 /omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0 { 309 pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_1)>; 310 }; 311 312 /omit-if-no-ref/ p0_3_pwm1_1: p0_3_pwm1_1 { 313 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_1)>; 314 }; 315 316 /omit-if-no-ref/ p0_5_pwm1_2: p0_5_pwm1_2 { 317 pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_1)>; 318 }; 319 320 /omit-if-no-ref/ p1_1_pwm1_3: p1_1_pwm1_3 { 321 pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_1)>; 322 }; 323 324 /omit-if-no-ref/ p1_3_pwm1_4: p1_3_pwm1_4 { 325 pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_1)>; 326 }; 327 328 /omit-if-no-ref/ p1_5_pwm1_5: p1_5_pwm1_5 { 329 pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_1)>; 330 }; 331 332 /omit-if-no-ref/ p3_0_pwm1_0: p3_0_pwm1_0 { 333 pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_1)>; 334 }; 335 336 /omit-if-no-ref/ p3_2_pwm1_1: p3_2_pwm1_1 { 337 pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_1)>; 338 }; 339 340 /omit-if-no-ref/ p3_4_pwm1_2: p3_4_pwm1_2 { 341 pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_1)>; 342 }; 343 344 /omit-if-no-ref/ p3_6_pwm1_3: p3_6_pwm1_3 { 345 pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_1)>; 346 }; 347 348 /omit-if-no-ref/ p4_1_pwm1_6: p4_1_pwm1_6 { 349 pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_1)>; 350 }; 351 352 /omit-if-no-ref/ p5_0_pwm1_4: p5_0_pwm1_4 { 353 pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_1)>; 354 }; 355 356 /omit-if-no-ref/ p5_2_pwm1_5: p5_2_pwm1_5 { 357 pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_1)>; 358 }; 359 }; 360 }; 361}; 362
