1/*
2 * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "cyw20829.dtsi"
11
12/ {
13	soc {
14
15		pinctrl: pinctrl@40400000 {
16			/* scb_i2c_scl */
17			/omit-if-no-ref/ p1_2_scb2_i2c_scl: p1_2_scb2_i2c_scl {
18				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_7)>;
19			};
20			/omit-if-no-ref/ p3_2_scb2_i2c_scl: p3_2_scb2_i2c_scl {
21				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_7)>;
22			};
23			/omit-if-no-ref/ p4_0_scb0_i2c_scl: p4_0_scb0_i2c_scl {
24				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_3)>;
25			};
26			/omit-if-no-ref/ p5_0_scb2_i2c_scl: p5_0_scb2_i2c_scl {
27				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
28			};
29
30			/* scb_i2c_sda */
31			/omit-if-no-ref/ p1_3_scb2_i2c_sda: p1_3_scb2_i2c_sda {
32				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_7)>;
33			};
34			/omit-if-no-ref/ p3_3_scb2_i2c_sda: p3_3_scb2_i2c_sda {
35				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_7)>;
36			};
37			/omit-if-no-ref/ p4_1_scb0_i2c_sda: p4_1_scb0_i2c_sda {
38				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_3)>;
39			};
40			/omit-if-no-ref/ p5_1_scb2_i2c_sda: p5_1_scb2_i2c_sda {
41				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
42			};
43
44			/* scb_spi_m_clk */
45			/omit-if-no-ref/ p0_4_scb0_spi_m_clk: p0_4_scb0_spi_m_clk {
46				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
47			};
48			/omit-if-no-ref/ p1_1_scb1_spi_m_clk: p1_1_scb1_spi_m_clk {
49				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
50			};
51			/omit-if-no-ref/ p3_1_scb1_spi_m_clk: p3_1_scb1_spi_m_clk {
52				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
53			};
54
55			/* scb_spi_m_miso */
56			/omit-if-no-ref/ p1_3_scb1_spi_m_miso: p1_3_scb1_spi_m_miso {
57				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
58			};
59			/omit-if-no-ref/ p3_3_scb1_spi_m_miso: p3_3_scb1_spi_m_miso {
60				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
61			};
62			/omit-if-no-ref/ p4_1_scb0_spi_m_miso: p4_1_scb0_spi_m_miso {
63				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
64			};
65
66			/* scb_spi_m_mosi */
67			/omit-if-no-ref/ p1_2_scb1_spi_m_mosi: p1_2_scb1_spi_m_mosi {
68				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
69			};
70			/omit-if-no-ref/ p3_2_scb1_spi_m_mosi: p3_2_scb1_spi_m_mosi {
71				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
72			};
73			/omit-if-no-ref/ p4_0_scb0_spi_m_mosi: p4_0_scb0_spi_m_mosi {
74				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
75			};
76
77			/* scb_spi_m_select0 */
78			/omit-if-no-ref/ p1_0_scb1_spi_m_select0: p1_0_scb1_spi_m_select0 {
79				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
80			};
81			/omit-if-no-ref/ p5_0_scb1_spi_m_select0: p5_0_scb1_spi_m_select0 {
82				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
83			};
84			/omit-if-no-ref/ p5_1_scb0_spi_m_select0: p5_1_scb0_spi_m_select0 {
85				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
86			};
87
88			/* scb_spi_m_select1 */
89			/omit-if-no-ref/ p0_5_scb1_spi_m_select1: p0_5_scb1_spi_m_select1 {
90				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
91			};
92
93			/* scb_spi_m_select2 */
94			/omit-if-no-ref/ p0_4_scb1_spi_m_select2: p0_4_scb1_spi_m_select2 {
95				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
96			};
97
98			/* scb_spi_m_select3 */
99
100			/* scb_spi_s_clk */
101			/omit-if-no-ref/ p0_4_scb0_spi_s_clk: p0_4_scb0_spi_s_clk {
102				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
103			};
104			/omit-if-no-ref/ p1_1_scb1_spi_s_clk: p1_1_scb1_spi_s_clk {
105				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
106			};
107			/omit-if-no-ref/ p3_1_scb1_spi_s_clk: p3_1_scb1_spi_s_clk {
108				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
109			};
110
111			/* scb_spi_s_miso */
112			/omit-if-no-ref/ p1_3_scb1_spi_s_miso: p1_3_scb1_spi_s_miso {
113				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
114			};
115			/omit-if-no-ref/ p3_3_scb1_spi_s_miso: p3_3_scb1_spi_s_miso {
116				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
117			};
118			/omit-if-no-ref/ p4_1_scb0_spi_s_miso: p4_1_scb0_spi_s_miso {
119				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
120			};
121
122			/* scb_spi_s_mosi */
123			/omit-if-no-ref/ p1_2_scb1_spi_s_mosi: p1_2_scb1_spi_s_mosi {
124				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
125			};
126			/omit-if-no-ref/ p3_2_scb1_spi_s_mosi: p3_2_scb1_spi_s_mosi {
127				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
128			};
129			/omit-if-no-ref/ p4_0_scb0_spi_s_mosi: p4_0_scb0_spi_s_mosi {
130				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
131			};
132
133			/* scb_spi_s_select0 */
134			/omit-if-no-ref/ p1_0_scb1_spi_s_select0: p1_0_scb1_spi_s_select0 {
135				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
136			};
137			/omit-if-no-ref/ p5_0_scb1_spi_s_select0: p5_0_scb1_spi_s_select0 {
138				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
139			};
140			/omit-if-no-ref/ p5_1_scb0_spi_s_select0: p5_1_scb0_spi_s_select0 {
141				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
142			};
143
144			/* scb_spi_s_select1 */
145			/omit-if-no-ref/ p0_5_scb1_spi_s_select1: p0_5_scb1_spi_s_select1 {
146				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
147			};
148
149			/* scb_spi_s_select2 */
150			/omit-if-no-ref/ p0_4_scb1_spi_s_select2: p0_4_scb1_spi_s_select2 {
151				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
152			};
153
154			/* scb_spi_s_select3 */
155
156			/* scb_uart_cts */
157			/omit-if-no-ref/ p1_0_scb1_uart_cts: p1_0_scb1_uart_cts {
158				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
159			};
160			/omit-if-no-ref/ p4_0_scb2_uart_cts: p4_0_scb2_uart_cts {
161				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
162			};
163			/omit-if-no-ref/ p5_0_scb2_uart_cts: p5_0_scb2_uart_cts {
164				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
165			};
166
167			/* scb_uart_rts */
168			/omit-if-no-ref/ p1_1_scb1_uart_rts: p1_1_scb1_uart_rts {
169				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
170			};
171			/omit-if-no-ref/ p3_1_scb2_uart_rts: p3_1_scb2_uart_rts {
172				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
173			};
174
175			/* scb_uart_rx */
176			/omit-if-no-ref/ p1_2_scb1_uart_rx: p1_2_scb1_uart_rx {
177				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
178			};
179			/omit-if-no-ref/ p3_2_scb2_uart_rx: p3_2_scb2_uart_rx {
180				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
181			};
182
183			/* scb_uart_tx */
184			/omit-if-no-ref/ p1_3_scb1_uart_tx: p1_3_scb1_uart_tx {
185				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
186			};
187			/omit-if-no-ref/ p3_3_scb2_uart_tx: p3_3_scb2_uart_tx {
188				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
189			};
190
191			/* PWM group 0 */
192			/omit-if-no-ref/ p0_1_pwm0_1: p0_1_pwm0_1 {
193				pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_0)>;
194			};
195
196			/omit-if-no-ref/ p0_3_pwm0_0: p0_3_pwm0_0 {
197				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_0)>;
198			};
199
200			/omit-if-no-ref/ p0_5_pwm0_1: p0_5_pwm0_1 {
201				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_0)>;
202			};
203
204			/omit-if-no-ref/ p1_1_pwm0_0: p1_1_pwm0_0 {
205				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_0)>;
206			};
207
208			/omit-if-no-ref/ p1_3_pwm0_1: p1_3_pwm0_1 {
209				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_0)>;
210			};
211
212			/omit-if-no-ref/ p1_5_pwm0_0: p1_5_pwm0_0 {
213				pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_0)>;
214			};
215
216			/omit-if-no-ref/ p3_0_pwm0_0: p3_0_pwm0_0 {
217				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_0)>;
218			};
219
220			/omit-if-no-ref/ p3_2_pwm0_1: p3_2_pwm0_1 {
221				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_0)>;
222			};
223
224			/omit-if-no-ref/ p3_4_pwm0_0: p3_4_pwm0_0 {
225				pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_0)>;
226			};
227
228			/omit-if-no-ref/ p3_6_pwm0_1: p3_6_pwm0_1 {
229				pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_0)>;
230			};
231
232			/omit-if-no-ref/ p4_1_pwm0_0: p4_1_pwm0_0 {
233				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_0)>;
234			};
235
236			/omit-if-no-ref/ p5_0_pwm0_0: p5_0_pwm0_0 {
237				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_0)>;
238			};
239
240			/omit-if-no-ref/ p5_2_pwm0_1: p5_2_pwm0_1 {
241				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_0)>;
242			};
243
244			/* PWM group 1 */
245			/omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0 {
246				pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_1)>;
247			};
248
249			/omit-if-no-ref/ p0_3_pwm1_1: p0_3_pwm1_1 {
250				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_1)>;
251			};
252
253			/omit-if-no-ref/ p0_5_pwm1_2: p0_5_pwm1_2 {
254				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_1)>;
255			};
256
257			/omit-if-no-ref/ p1_1_pwm1_3: p1_1_pwm1_3 {
258				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_1)>;
259			};
260
261			/omit-if-no-ref/ p1_3_pwm1_4: p1_3_pwm1_4 {
262				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_1)>;
263			};
264
265			/omit-if-no-ref/ p1_5_pwm1_5: p1_5_pwm1_5 {
266				pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_1)>;
267			};
268
269			/omit-if-no-ref/ p3_0_pwm1_0: p3_0_pwm1_0 {
270				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_1)>;
271			};
272
273			/omit-if-no-ref/ p3_2_pwm1_1: p3_2_pwm1_1 {
274				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_1)>;
275			};
276
277			/omit-if-no-ref/ p3_4_pwm1_2: p3_4_pwm1_2 {
278				pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_1)>;
279			};
280
281			/omit-if-no-ref/ p3_6_pwm1_3: p3_6_pwm1_3 {
282				pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_1)>;
283			};
284
285			/omit-if-no-ref/ p4_1_pwm1_6: p4_1_pwm1_6 {
286				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_1)>;
287			};
288
289			/omit-if-no-ref/ p5_0_pwm1_4: p5_0_pwm1_4 {
290				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_1)>;
291			};
292
293			/omit-if-no-ref/ p5_2_pwm1_5: p5_2_pwm1_5 {
294				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_1)>;
295			};
296		};
297	};
298};
299
300&gpio_prt0 {
301	ngpios = <2>;
302};
303&gpio_prt1 {
304	ngpios = <4>;
305};
306&gpio_prt3 {
307	ngpios = <3>;
308};
309&gpio_prt5 {
310	ngpios = <2>;
311};
312