1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_04.dtsi"
11
12/ {
13	soc {
14		/delete-node/ gpio@40310080; // gpio_prt1
15		/delete-node/ gpio@40310200; // gpio_prt4
16		/delete-node/ gpio@40310680; // gpio_prt13
17		/delete-node/ gpio@40310700; // gpio_prt14
18
19		pinctrl: pinctrl@40300000 {
20			/* scb_i2c_scl */
21			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
22				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
23			};
24			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
25				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
26			};
27			/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
28				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
29			};
30			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
31				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
32			};
33			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
34				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
35			};
36			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
37				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
38			};
39			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
40				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
41			};
42			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
43				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
44			};
45			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
46				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
47			};
48
49			/* scb_i2c_sda */
50			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
51				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
52			};
53			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
54				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
55			};
56			/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
57				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
58			};
59			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
60				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
61			};
62			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
63				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
64			};
65			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
66				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
67			};
68			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
69				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
70			};
71			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
72				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
73			};
74			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
75				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
76			};
77
78			/* scb_uart_cts */
79			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
80				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
81			};
82			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
83				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
84			};
85			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
86				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
87			};
88			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
89				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
90			};
91			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
92				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
93			};
94			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
95				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
96			};
97
98			/* scb_uart_rts */
99			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
100				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
101			};
102			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
103				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
104			};
105			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
106				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
107			};
108			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
109				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
110			};
111			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
112				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
113			};
114			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
115				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
116			};
117
118			/* scb_uart_rx */
119			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
120				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
121			};
122			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
123				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
124			};
125			/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
126				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
127			};
128			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
129				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
130			};
131			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
132				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
133			};
134			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
135				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
136			};
137			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
138				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
139			};
140			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
141				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
142			};
143
144			/* scb_uart_tx */
145			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
146				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
147			};
148			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
149				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
150			};
151			/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
152				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
153			};
154			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
155				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
156			};
157			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
158				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
159			};
160			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
161				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
162			};
163			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
164				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
165			};
166			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
167				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
168			};
169
170		};
171	};
172};
173