1/* 2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <zephyr/dt-bindings/gpio/gpio.h> 9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h> 10#include "psoc6_01.dtsi" 11 12/ { 13 soc { 14 /delete-node/ gpio@40320080; // gpio_prt1 15 /delete-node/ gpio@40320100; // gpio_prt2 16 /delete-node/ gpio@40320180; // gpio_prt3 17 /delete-node/ gpio@40320200; // gpio_prt4 18 /delete-node/ gpio@40320280; // gpio_prt5 19 /delete-node/ gpio@40320680; // gpio_prt13 20 /delete-node/ gpio@40320700; // gpio_prt14 21 22 pinctrl: pinctrl@40310000 { 23 /* scb_i2c_scl */ 24 /omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl { 25 pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>; 26 }; 27 /omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl { 28 pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>; 29 }; 30 /omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl { 31 pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>; 32 }; 33 /omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl { 34 pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>; 35 }; 36 /omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl { 37 pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>; 38 }; 39 /omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl { 40 pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>; 41 }; 42 /omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl { 43 pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>; 44 }; 45 /omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl { 46 pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>; 47 }; 48 /omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl { 49 pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>; 50 }; 51 /omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl { 52 pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>; 53 }; 54 55 /* scb_i2c_sda */ 56 /omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda { 57 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>; 58 }; 59 /omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda { 60 pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>; 61 }; 62 /omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda { 63 pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>; 64 }; 65 /omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda { 66 pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>; 67 }; 68 /omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda { 69 pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>; 70 }; 71 /omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda { 72 pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>; 73 }; 74 /omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda { 75 pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>; 76 }; 77 /omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda { 78 pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>; 79 }; 80 /omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda { 81 pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>; 82 }; 83 /omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda { 84 pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>; 85 }; 86 87 /* scb_uart_cts */ 88 /omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts { 89 pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>; 90 }; 91 /omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts { 92 pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>; 93 }; 94 /omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts { 95 pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>; 96 }; 97 /omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts { 98 pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>; 99 }; 100 /omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts { 101 pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>; 102 }; 103 /omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts { 104 pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>; 105 }; 106 107 /* scb_uart_rts */ 108 /omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts { 109 pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>; 110 }; 111 /omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts { 112 pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>; 113 }; 114 /omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts { 115 pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>; 116 }; 117 /omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts { 118 pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>; 119 }; 120 /omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts { 121 pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>; 122 }; 123 /omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts { 124 pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>; 125 }; 126 /omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts { 127 pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>; 128 }; 129 130 /* scb_uart_rx */ 131 /omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx { 132 pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>; 133 }; 134 /omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx { 135 pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>; 136 }; 137 /omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx { 138 pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>; 139 }; 140 /omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx { 141 pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>; 142 }; 143 /omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx { 144 pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>; 145 }; 146 /omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx { 147 pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>; 148 }; 149 /omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx { 150 pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>; 151 }; 152 /omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx { 153 pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>; 154 }; 155 156 /* scb_uart_tx */ 157 /omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx { 158 pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>; 159 }; 160 /omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx { 161 pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>; 162 }; 163 /omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx { 164 pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>; 165 }; 166 /omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx { 167 pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>; 168 }; 169 /omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx { 170 pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>; 171 }; 172 /omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx { 173 pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>; 174 }; 175 /omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx { 176 pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>; 177 }; 178 /omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx { 179 pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>; 180 }; 181 182 }; 183 }; 184}; 185
