1/*
2 * Copyright (c) 2021 ATL Electronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/gpio/gpio.h>
8#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
9
10/ {
11	soc {
12
13		pinctrl: pinctrl@40310000 {
14			/* scb_i2c_scl */
15			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
16				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
17			};
18			/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
19				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
20			};
21			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
22				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
23			};
24			/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
25				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
26			};
27			/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
28				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
29			};
30			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
31				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
32			};
33			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
34				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
35			};
36			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
37				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
38			};
39			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
40				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
41			};
42			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
43				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
44			};
45			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
46				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
47			};
48			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
49				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
50			};
51			/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
52				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
53			};
54			/omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl {
55				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_7)>;
56			};
57
58			/* scb_i2c_sda */
59			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
60				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
61			};
62			/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
63				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
64			};
65			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
66				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
67			};
68			/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
69				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
70			};
71			/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
72				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
73			};
74			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
75				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
76			};
77			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
78				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
79			};
80			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
81				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
82			};
83			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
84				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
85			};
86			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
87				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
88			};
89			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
90				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
91			};
92			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
93				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
94			};
95			/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
96				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
97			};
98			/omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda {
99				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_7)>;
100			};
101
102			/* scb_spi_m_clk */
103			/omit-if-no-ref/ p0_4_scb0_spi_m_clk: p0_4_scb0_spi_m_clk {
104				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
105			};
106			/omit-if-no-ref/ p5_2_scb5_spi_m_clk: p5_2_scb5_spi_m_clk {
107				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_8)>;
108			};
109			/omit-if-no-ref/ p6_2_scb3_spi_m_clk: p6_2_scb3_spi_m_clk {
110				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_8)>;
111			};
112			/omit-if-no-ref/ p6_2_scb8_spi_m_clk: p6_2_scb8_spi_m_clk {
113				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_DS_6)>;
114			};
115			/omit-if-no-ref/ p6_6_scb6_spi_m_clk: p6_6_scb6_spi_m_clk {
116				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_8)>;
117			};
118			/omit-if-no-ref/ p6_6_scb8_spi_m_clk: p6_6_scb8_spi_m_clk {
119				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_DS_6)>;
120			};
121			/omit-if-no-ref/ p7_2_scb4_spi_m_clk: p7_2_scb4_spi_m_clk {
122				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_8)>;
123			};
124			/omit-if-no-ref/ p8_2_scb4_spi_m_clk: p8_2_scb4_spi_m_clk {
125				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_8)>;
126			};
127			/omit-if-no-ref/ p9_2_scb2_spi_m_clk: p9_2_scb2_spi_m_clk {
128				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_8)>;
129			};
130			/omit-if-no-ref/ p10_2_scb1_spi_m_clk: p10_2_scb1_spi_m_clk {
131				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_8)>;
132			};
133			/omit-if-no-ref/ p11_2_scb5_spi_m_clk: p11_2_scb5_spi_m_clk {
134				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_8)>;
135			};
136			/omit-if-no-ref/ p12_2_scb6_spi_m_clk: p12_2_scb6_spi_m_clk {
137				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_8)>;
138			};
139
140			/* scb_spi_m_miso */
141			/omit-if-no-ref/ p0_3_scb0_spi_m_miso: p0_3_scb0_spi_m_miso {
142				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>;
143			};
144			/omit-if-no-ref/ p1_1_scb7_spi_m_miso: p1_1_scb7_spi_m_miso {
145				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
146			};
147			/omit-if-no-ref/ p5_1_scb5_spi_m_miso: p5_1_scb5_spi_m_miso {
148				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_8)>;
149			};
150			/omit-if-no-ref/ p6_1_scb3_spi_m_miso: p6_1_scb3_spi_m_miso {
151				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_8)>;
152			};
153			/omit-if-no-ref/ p6_1_scb8_spi_m_miso: p6_1_scb8_spi_m_miso {
154				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_6)>;
155			};
156			/omit-if-no-ref/ p6_5_scb6_spi_m_miso: p6_5_scb6_spi_m_miso {
157				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_8)>;
158			};
159			/omit-if-no-ref/ p6_5_scb8_spi_m_miso: p6_5_scb8_spi_m_miso {
160				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_6)>;
161			};
162			/omit-if-no-ref/ p7_1_scb4_spi_m_miso: p7_1_scb4_spi_m_miso {
163				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_8)>;
164			};
165			/omit-if-no-ref/ p8_1_scb4_spi_m_miso: p8_1_scb4_spi_m_miso {
166				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_8)>;
167			};
168			/omit-if-no-ref/ p9_1_scb2_spi_m_miso: p9_1_scb2_spi_m_miso {
169				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_8)>;
170			};
171			/omit-if-no-ref/ p10_1_scb1_spi_m_miso: p10_1_scb1_spi_m_miso {
172				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_8)>;
173			};
174			/omit-if-no-ref/ p11_1_scb5_spi_m_miso: p11_1_scb5_spi_m_miso {
175				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_8)>;
176			};
177			/omit-if-no-ref/ p12_1_scb6_spi_m_miso: p12_1_scb6_spi_m_miso {
178				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_8)>;
179			};
180			/omit-if-no-ref/ p13_1_scb6_spi_m_miso: p13_1_scb6_spi_m_miso {
181				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_8)>;
182			};
183
184			/* scb_spi_m_mosi */
185			/omit-if-no-ref/ p0_2_scb0_spi_m_mosi: p0_2_scb0_spi_m_mosi {
186				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_8)>;
187			};
188			/omit-if-no-ref/ p1_0_scb7_spi_m_mosi: p1_0_scb7_spi_m_mosi {
189				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
190			};
191			/omit-if-no-ref/ p5_0_scb5_spi_m_mosi: p5_0_scb5_spi_m_mosi {
192				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
193			};
194			/omit-if-no-ref/ p6_0_scb3_spi_m_mosi: p6_0_scb3_spi_m_mosi {
195				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_8)>;
196			};
197			/omit-if-no-ref/ p6_0_scb8_spi_m_mosi: p6_0_scb8_spi_m_mosi {
198				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_6)>;
199			};
200			/omit-if-no-ref/ p6_4_scb6_spi_m_mosi: p6_4_scb6_spi_m_mosi {
201				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_8)>;
202			};
203			/omit-if-no-ref/ p6_4_scb8_spi_m_mosi: p6_4_scb8_spi_m_mosi {
204				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_6)>;
205			};
206			/omit-if-no-ref/ p7_0_scb4_spi_m_mosi: p7_0_scb4_spi_m_mosi {
207				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_8)>;
208			};
209			/omit-if-no-ref/ p8_0_scb4_spi_m_mosi: p8_0_scb4_spi_m_mosi {
210				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_8)>;
211			};
212			/omit-if-no-ref/ p9_0_scb2_spi_m_mosi: p9_0_scb2_spi_m_mosi {
213				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_8)>;
214			};
215			/omit-if-no-ref/ p10_0_scb1_spi_m_mosi: p10_0_scb1_spi_m_mosi {
216				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_8)>;
217			};
218			/omit-if-no-ref/ p11_0_scb5_spi_m_mosi: p11_0_scb5_spi_m_mosi {
219				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_8)>;
220			};
221			/omit-if-no-ref/ p12_0_scb6_spi_m_mosi: p12_0_scb6_spi_m_mosi {
222				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_8)>;
223			};
224			/omit-if-no-ref/ p13_0_scb6_spi_m_mosi: p13_0_scb6_spi_m_mosi {
225				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_8)>;
226			};
227
228			/* scb_spi_m_select0 */
229			/omit-if-no-ref/ p0_5_scb0_spi_m_select0: p0_5_scb0_spi_m_select0 {
230				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
231			};
232			/omit-if-no-ref/ p5_3_scb5_spi_m_select0: p5_3_scb5_spi_m_select0 {
233				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_8)>;
234			};
235			/omit-if-no-ref/ p6_3_scb3_spi_m_select0: p6_3_scb3_spi_m_select0 {
236				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_8)>;
237			};
238			/omit-if-no-ref/ p6_3_scb8_spi_m_select0: p6_3_scb8_spi_m_select0 {
239				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_DS_6)>;
240			};
241			/omit-if-no-ref/ p6_7_scb6_spi_m_select0: p6_7_scb6_spi_m_select0 {
242				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_8)>;
243			};
244			/omit-if-no-ref/ p6_7_scb8_spi_m_select0: p6_7_scb8_spi_m_select0 {
245				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_DS_6)>;
246			};
247			/omit-if-no-ref/ p7_3_scb4_spi_m_select0: p7_3_scb4_spi_m_select0 {
248				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_8)>;
249			};
250			/omit-if-no-ref/ p8_3_scb4_spi_m_select0: p8_3_scb4_spi_m_select0 {
251				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_8)>;
252			};
253			/omit-if-no-ref/ p9_3_scb2_spi_m_select0: p9_3_scb2_spi_m_select0 {
254				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_8)>;
255			};
256			/omit-if-no-ref/ p10_3_scb1_spi_m_select0: p10_3_scb1_spi_m_select0 {
257				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_8)>;
258			};
259			/omit-if-no-ref/ p11_3_scb5_spi_m_select0: p11_3_scb5_spi_m_select0 {
260				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_8)>;
261			};
262			/omit-if-no-ref/ p12_3_scb6_spi_m_select0: p12_3_scb6_spi_m_select0 {
263				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_8)>;
264			};
265
266			/* scb_spi_m_select1 */
267			/omit-if-no-ref/ p0_0_scb0_spi_m_select1: p0_0_scb0_spi_m_select1 {
268				pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_ACT_8)>;
269			};
270			/omit-if-no-ref/ p1_4_scb7_spi_m_select1: p1_4_scb7_spi_m_select1 {
271				pinmux = <DT_CAT1_PINMUX(1, 4, HSIOM_SEL_ACT_8)>;
272			};
273			/omit-if-no-ref/ p5_4_scb5_spi_m_select1: p5_4_scb5_spi_m_select1 {
274				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_8)>;
275			};
276			/omit-if-no-ref/ p7_4_scb4_spi_m_select1: p7_4_scb4_spi_m_select1 {
277				pinmux = <DT_CAT1_PINMUX(7, 4, HSIOM_SEL_ACT_8)>;
278			};
279			/omit-if-no-ref/ p7_7_scb3_spi_m_select1: p7_7_scb3_spi_m_select1 {
280				pinmux = <DT_CAT1_PINMUX(7, 7, HSIOM_SEL_ACT_8)>;
281			};
282			/omit-if-no-ref/ p8_4_scb4_spi_m_select1: p8_4_scb4_spi_m_select1 {
283				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_8)>;
284			};
285			/omit-if-no-ref/ p10_4_scb1_spi_m_select1: p10_4_scb1_spi_m_select1 {
286				pinmux = <DT_CAT1_PINMUX(10, 4, HSIOM_SEL_ACT_8)>;
287			};
288			/omit-if-no-ref/ p11_4_scb5_spi_m_select1: p11_4_scb5_spi_m_select1 {
289				pinmux = <DT_CAT1_PINMUX(11, 4, HSIOM_SEL_ACT_8)>;
290			};
291			/omit-if-no-ref/ p12_4_scb6_spi_m_select1: p12_4_scb6_spi_m_select1 {
292				pinmux = <DT_CAT1_PINMUX(12, 4, HSIOM_SEL_ACT_8)>;
293			};
294
295			/* scb_spi_m_select2 */
296			/omit-if-no-ref/ p0_1_scb0_spi_m_select2: p0_1_scb0_spi_m_select2 {
297				pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_8)>;
298			};
299			/omit-if-no-ref/ p1_5_scb7_spi_m_select2: p1_5_scb7_spi_m_select2 {
300				pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_8)>;
301			};
302			/omit-if-no-ref/ p5_5_scb5_spi_m_select2: p5_5_scb5_spi_m_select2 {
303				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_8)>;
304			};
305			/omit-if-no-ref/ p7_5_scb4_spi_m_select2: p7_5_scb4_spi_m_select2 {
306				pinmux = <DT_CAT1_PINMUX(7, 5, HSIOM_SEL_ACT_8)>;
307			};
308			/omit-if-no-ref/ p8_5_scb4_spi_m_select2: p8_5_scb4_spi_m_select2 {
309				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_8)>;
310			};
311			/omit-if-no-ref/ p8_7_scb3_spi_m_select2: p8_7_scb3_spi_m_select2 {
312				pinmux = <DT_CAT1_PINMUX(8, 7, HSIOM_SEL_ACT_8)>;
313			};
314			/omit-if-no-ref/ p10_5_scb1_spi_m_select2: p10_5_scb1_spi_m_select2 {
315				pinmux = <DT_CAT1_PINMUX(10, 5, HSIOM_SEL_ACT_8)>;
316			};
317			/omit-if-no-ref/ p11_5_scb5_spi_m_select2: p11_5_scb5_spi_m_select2 {
318				pinmux = <DT_CAT1_PINMUX(11, 5, HSIOM_SEL_ACT_8)>;
319			};
320
321			/* scb_spi_m_select3 */
322			/omit-if-no-ref/ p5_6_scb5_spi_m_select3: p5_6_scb5_spi_m_select3 {
323				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_8)>;
324			};
325			/omit-if-no-ref/ p5_7_scb3_spi_m_select3: p5_7_scb3_spi_m_select3 {
326				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_8)>;
327			};
328			/omit-if-no-ref/ p7_6_scb4_spi_m_select3: p7_6_scb4_spi_m_select3 {
329				pinmux = <DT_CAT1_PINMUX(7, 6, HSIOM_SEL_ACT_8)>;
330			};
331			/omit-if-no-ref/ p8_6_scb4_spi_m_select3: p8_6_scb4_spi_m_select3 {
332				pinmux = <DT_CAT1_PINMUX(8, 6, HSIOM_SEL_ACT_8)>;
333			};
334			/omit-if-no-ref/ p10_6_scb1_spi_m_select3: p10_6_scb1_spi_m_select3 {
335				pinmux = <DT_CAT1_PINMUX(10, 6, HSIOM_SEL_ACT_8)>;
336			};
337			/omit-if-no-ref/ p11_6_scb5_spi_m_select3: p11_6_scb5_spi_m_select3 {
338				pinmux = <DT_CAT1_PINMUX(11, 6, HSIOM_SEL_ACT_8)>;
339			};
340
341			/* scb_spi_s_clk */
342			/omit-if-no-ref/ p0_4_scb0_spi_s_clk: p0_4_scb0_spi_s_clk {
343				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
344			};
345			/omit-if-no-ref/ p5_2_scb5_spi_s_clk: p5_2_scb5_spi_s_clk {
346				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_8)>;
347			};
348			/omit-if-no-ref/ p6_2_scb3_spi_s_clk: p6_2_scb3_spi_s_clk {
349				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_8)>;
350			};
351			/omit-if-no-ref/ p6_2_scb8_spi_s_clk: p6_2_scb8_spi_s_clk {
352				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_DS_6)>;
353			};
354			/omit-if-no-ref/ p6_6_scb6_spi_s_clk: p6_6_scb6_spi_s_clk {
355				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_8)>;
356			};
357			/omit-if-no-ref/ p6_6_scb8_spi_s_clk: p6_6_scb8_spi_s_clk {
358				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_DS_6)>;
359			};
360			/omit-if-no-ref/ p7_2_scb4_spi_s_clk: p7_2_scb4_spi_s_clk {
361				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_8)>;
362			};
363			/omit-if-no-ref/ p8_2_scb4_spi_s_clk: p8_2_scb4_spi_s_clk {
364				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_8)>;
365			};
366			/omit-if-no-ref/ p9_2_scb2_spi_s_clk: p9_2_scb2_spi_s_clk {
367				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_8)>;
368			};
369			/omit-if-no-ref/ p10_2_scb1_spi_s_clk: p10_2_scb1_spi_s_clk {
370				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_8)>;
371			};
372			/omit-if-no-ref/ p11_2_scb5_spi_s_clk: p11_2_scb5_spi_s_clk {
373				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_8)>;
374			};
375			/omit-if-no-ref/ p12_2_scb6_spi_s_clk: p12_2_scb6_spi_s_clk {
376				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_8)>;
377			};
378
379			/* scb_spi_s_miso */
380			/omit-if-no-ref/ p0_3_scb0_spi_s_miso: p0_3_scb0_spi_s_miso {
381				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>;
382			};
383			/omit-if-no-ref/ p1_1_scb7_spi_s_miso: p1_1_scb7_spi_s_miso {
384				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
385			};
386			/omit-if-no-ref/ p5_1_scb5_spi_s_miso: p5_1_scb5_spi_s_miso {
387				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_8)>;
388			};
389			/omit-if-no-ref/ p6_1_scb3_spi_s_miso: p6_1_scb3_spi_s_miso {
390				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_8)>;
391			};
392			/omit-if-no-ref/ p6_1_scb8_spi_s_miso: p6_1_scb8_spi_s_miso {
393				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_6)>;
394			};
395			/omit-if-no-ref/ p6_5_scb6_spi_s_miso: p6_5_scb6_spi_s_miso {
396				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_8)>;
397			};
398			/omit-if-no-ref/ p6_5_scb8_spi_s_miso: p6_5_scb8_spi_s_miso {
399				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_6)>;
400			};
401			/omit-if-no-ref/ p7_1_scb4_spi_s_miso: p7_1_scb4_spi_s_miso {
402				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_8)>;
403			};
404			/omit-if-no-ref/ p8_1_scb4_spi_s_miso: p8_1_scb4_spi_s_miso {
405				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_8)>;
406			};
407			/omit-if-no-ref/ p9_1_scb2_spi_s_miso: p9_1_scb2_spi_s_miso {
408				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_8)>;
409			};
410			/omit-if-no-ref/ p10_1_scb1_spi_s_miso: p10_1_scb1_spi_s_miso {
411				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_8)>;
412			};
413			/omit-if-no-ref/ p11_1_scb5_spi_s_miso: p11_1_scb5_spi_s_miso {
414				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_8)>;
415			};
416			/omit-if-no-ref/ p12_1_scb6_spi_s_miso: p12_1_scb6_spi_s_miso {
417				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_8)>;
418			};
419			/omit-if-no-ref/ p13_1_scb6_spi_s_miso: p13_1_scb6_spi_s_miso {
420				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_8)>;
421			};
422
423			/* scb_spi_s_mosi */
424			/omit-if-no-ref/ p0_2_scb0_spi_s_mosi: p0_2_scb0_spi_s_mosi {
425				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_8)>;
426			};
427			/omit-if-no-ref/ p1_0_scb7_spi_s_mosi: p1_0_scb7_spi_s_mosi {
428				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
429			};
430			/omit-if-no-ref/ p5_0_scb5_spi_s_mosi: p5_0_scb5_spi_s_mosi {
431				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
432			};
433			/omit-if-no-ref/ p6_0_scb3_spi_s_mosi: p6_0_scb3_spi_s_mosi {
434				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_8)>;
435			};
436			/omit-if-no-ref/ p6_0_scb8_spi_s_mosi: p6_0_scb8_spi_s_mosi {
437				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_6)>;
438			};
439			/omit-if-no-ref/ p6_4_scb6_spi_s_mosi: p6_4_scb6_spi_s_mosi {
440				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_8)>;
441			};
442			/omit-if-no-ref/ p6_4_scb8_spi_s_mosi: p6_4_scb8_spi_s_mosi {
443				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_6)>;
444			};
445			/omit-if-no-ref/ p7_0_scb4_spi_s_mosi: p7_0_scb4_spi_s_mosi {
446				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_8)>;
447			};
448			/omit-if-no-ref/ p8_0_scb4_spi_s_mosi: p8_0_scb4_spi_s_mosi {
449				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_8)>;
450			};
451			/omit-if-no-ref/ p9_0_scb2_spi_s_mosi: p9_0_scb2_spi_s_mosi {
452				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_8)>;
453			};
454			/omit-if-no-ref/ p10_0_scb1_spi_s_mosi: p10_0_scb1_spi_s_mosi {
455				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_8)>;
456			};
457			/omit-if-no-ref/ p11_0_scb5_spi_s_mosi: p11_0_scb5_spi_s_mosi {
458				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_8)>;
459			};
460			/omit-if-no-ref/ p12_0_scb6_spi_s_mosi: p12_0_scb6_spi_s_mosi {
461				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_8)>;
462			};
463			/omit-if-no-ref/ p13_0_scb6_spi_s_mosi: p13_0_scb6_spi_s_mosi {
464				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_8)>;
465			};
466
467			/* scb_spi_s_select0 */
468			/omit-if-no-ref/ p0_5_scb0_spi_s_select0: p0_5_scb0_spi_s_select0 {
469				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
470			};
471			/omit-if-no-ref/ p5_3_scb5_spi_s_select0: p5_3_scb5_spi_s_select0 {
472				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_8)>;
473			};
474			/omit-if-no-ref/ p6_3_scb3_spi_s_select0: p6_3_scb3_spi_s_select0 {
475				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_8)>;
476			};
477			/omit-if-no-ref/ p6_3_scb8_spi_s_select0: p6_3_scb8_spi_s_select0 {
478				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_DS_6)>;
479			};
480			/omit-if-no-ref/ p6_7_scb6_spi_s_select0: p6_7_scb6_spi_s_select0 {
481				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_8)>;
482			};
483			/omit-if-no-ref/ p6_7_scb8_spi_s_select0: p6_7_scb8_spi_s_select0 {
484				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_DS_6)>;
485			};
486			/omit-if-no-ref/ p7_3_scb4_spi_s_select0: p7_3_scb4_spi_s_select0 {
487				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_8)>;
488			};
489			/omit-if-no-ref/ p8_3_scb4_spi_s_select0: p8_3_scb4_spi_s_select0 {
490				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_8)>;
491			};
492			/omit-if-no-ref/ p9_3_scb2_spi_s_select0: p9_3_scb2_spi_s_select0 {
493				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_8)>;
494			};
495			/omit-if-no-ref/ p10_3_scb1_spi_s_select0: p10_3_scb1_spi_s_select0 {
496				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_8)>;
497			};
498			/omit-if-no-ref/ p11_3_scb5_spi_s_select0: p11_3_scb5_spi_s_select0 {
499				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_8)>;
500			};
501			/omit-if-no-ref/ p12_3_scb6_spi_s_select0: p12_3_scb6_spi_s_select0 {
502				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_8)>;
503			};
504
505			/* scb_spi_s_select1 */
506			/omit-if-no-ref/ p0_0_scb0_spi_s_select1: p0_0_scb0_spi_s_select1 {
507				pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_ACT_8)>;
508			};
509			/omit-if-no-ref/ p1_4_scb7_spi_s_select1: p1_4_scb7_spi_s_select1 {
510				pinmux = <DT_CAT1_PINMUX(1, 4, HSIOM_SEL_ACT_8)>;
511			};
512			/omit-if-no-ref/ p5_4_scb5_spi_s_select1: p5_4_scb5_spi_s_select1 {
513				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_8)>;
514			};
515			/omit-if-no-ref/ p7_4_scb4_spi_s_select1: p7_4_scb4_spi_s_select1 {
516				pinmux = <DT_CAT1_PINMUX(7, 4, HSIOM_SEL_ACT_8)>;
517			};
518			/omit-if-no-ref/ p7_7_scb3_spi_s_select1: p7_7_scb3_spi_s_select1 {
519				pinmux = <DT_CAT1_PINMUX(7, 7, HSIOM_SEL_ACT_8)>;
520			};
521			/omit-if-no-ref/ p8_4_scb4_spi_s_select1: p8_4_scb4_spi_s_select1 {
522				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_8)>;
523			};
524			/omit-if-no-ref/ p10_4_scb1_spi_s_select1: p10_4_scb1_spi_s_select1 {
525				pinmux = <DT_CAT1_PINMUX(10, 4, HSIOM_SEL_ACT_8)>;
526			};
527			/omit-if-no-ref/ p11_4_scb5_spi_s_select1: p11_4_scb5_spi_s_select1 {
528				pinmux = <DT_CAT1_PINMUX(11, 4, HSIOM_SEL_ACT_8)>;
529			};
530			/omit-if-no-ref/ p12_4_scb6_spi_s_select1: p12_4_scb6_spi_s_select1 {
531				pinmux = <DT_CAT1_PINMUX(12, 4, HSIOM_SEL_ACT_8)>;
532			};
533
534			/* scb_spi_s_select2 */
535			/omit-if-no-ref/ p0_1_scb0_spi_s_select2: p0_1_scb0_spi_s_select2 {
536				pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_8)>;
537			};
538			/omit-if-no-ref/ p1_5_scb7_spi_s_select2: p1_5_scb7_spi_s_select2 {
539				pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_8)>;
540			};
541			/omit-if-no-ref/ p5_5_scb5_spi_s_select2: p5_5_scb5_spi_s_select2 {
542				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_8)>;
543			};
544			/omit-if-no-ref/ p7_5_scb4_spi_s_select2: p7_5_scb4_spi_s_select2 {
545				pinmux = <DT_CAT1_PINMUX(7, 5, HSIOM_SEL_ACT_8)>;
546			};
547			/omit-if-no-ref/ p8_5_scb4_spi_s_select2: p8_5_scb4_spi_s_select2 {
548				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_8)>;
549			};
550			/omit-if-no-ref/ p8_7_scb3_spi_s_select2: p8_7_scb3_spi_s_select2 {
551				pinmux = <DT_CAT1_PINMUX(8, 7, HSIOM_SEL_ACT_8)>;
552			};
553			/omit-if-no-ref/ p10_5_scb1_spi_s_select2: p10_5_scb1_spi_s_select2 {
554				pinmux = <DT_CAT1_PINMUX(10, 5, HSIOM_SEL_ACT_8)>;
555			};
556			/omit-if-no-ref/ p11_5_scb5_spi_s_select2: p11_5_scb5_spi_s_select2 {
557				pinmux = <DT_CAT1_PINMUX(11, 5, HSIOM_SEL_ACT_8)>;
558			};
559
560			/* scb_spi_s_select3 */
561			/omit-if-no-ref/ p5_6_scb5_spi_s_select3: p5_6_scb5_spi_s_select3 {
562				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_8)>;
563			};
564			/omit-if-no-ref/ p5_7_scb3_spi_s_select3: p5_7_scb3_spi_s_select3 {
565				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_8)>;
566			};
567			/omit-if-no-ref/ p7_6_scb4_spi_s_select3: p7_6_scb4_spi_s_select3 {
568				pinmux = <DT_CAT1_PINMUX(7, 6, HSIOM_SEL_ACT_8)>;
569			};
570			/omit-if-no-ref/ p8_6_scb4_spi_s_select3: p8_6_scb4_spi_s_select3 {
571				pinmux = <DT_CAT1_PINMUX(8, 6, HSIOM_SEL_ACT_8)>;
572			};
573			/omit-if-no-ref/ p10_6_scb1_spi_s_select3: p10_6_scb1_spi_s_select3 {
574				pinmux = <DT_CAT1_PINMUX(10, 6, HSIOM_SEL_ACT_8)>;
575			};
576			/omit-if-no-ref/ p11_6_scb5_spi_s_select3: p11_6_scb5_spi_s_select3 {
577				pinmux = <DT_CAT1_PINMUX(11, 6, HSIOM_SEL_ACT_8)>;
578			};
579
580			/* scb_uart_cts */
581			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
582				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
583			};
584			/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
585				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
586			};
587			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
588				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
589			};
590			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
591				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
592			};
593			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
594				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
595			};
596			/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
597				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
598			};
599			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
600				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
601			};
602			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
603				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
604			};
605			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
606				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
607			};
608			/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
609				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
610			};
611
612			/* scb_uart_rts */
613			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
614				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
615			};
616			/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
617				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
618			};
619			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
620				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
621			};
622			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
623				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
624			};
625			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
626				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
627			};
628			/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
629				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
630			};
631			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
632				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
633			};
634			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
635				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
636			};
637			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
638				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
639			};
640			/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
641				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
642			};
643
644			/* scb_uart_rx */
645			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
646				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
647			};
648			/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
649				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
650			};
651			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
652				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
653			};
654			/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
655				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
656			};
657			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
658				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
659			};
660			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
661				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
662			};
663			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
664				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
665			};
666			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
667				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
668			};
669			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
670				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
671			};
672			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
673				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
674			};
675			/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
676				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
677			};
678			/omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx {
679				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_6)>;
680			};
681
682			/* scb_uart_tx */
683			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
684				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
685			};
686			/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
687				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
688			};
689			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
690				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
691			};
692			/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
693				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
694			};
695			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
696				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
697			};
698			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
699				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
700			};
701			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
702				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
703			};
704			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
705				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
706			};
707			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
708				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
709			};
710			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
711				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
712			};
713			/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
714				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
715			};
716			/omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx {
717				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_6)>;
718			};
719		};
720	};
721};
722