1/*
2 * Copyright (c) 2019 ML!PA Consulting GmbH
3 * Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13
14/ {
15	aliases {
16		adc-0 = &adc0;
17		adc-1 = &adc1;
18
19		port-a = &porta;
20		port-b = &portb;
21		port-c = &portc;
22		port-d = &portd;
23
24		rtc = &rtc;
25
26		sercom-0 = &sercom0;
27		sercom-1 = &sercom1;
28		sercom-2 = &sercom2;
29		sercom-3 = &sercom3;
30		sercom-4 = &sercom4;
31		sercom-5 = &sercom5;
32		sercom-6 = &sercom6;
33		sercom-7 = &sercom7;
34
35		tc-0 = &tc0;
36		tc-2 = &tc2;
37		tc-4 = &tc4;
38		tc-6 = &tc6;
39
40		tcc-0 = &tcc0;
41		tcc-1 = &tcc1;
42		tcc-2 = &tcc2;
43		tcc-3 = &tcc3;
44		tcc-4 = &tcc4;
45
46		watchdog0 = &wdog;
47	};
48
49	chosen {
50		zephyr,flash-controller = &nvmctrl;
51		zephyr,entropy = &trng;
52		zephyr,flash-controller = &nvmctrl;
53	};
54
55	cpus {
56		#address-cells = <1>;
57		#size-cells = <0>;
58
59		cpu0: cpu@0 {
60			compatible = "arm,cortex-m4f";
61			reg = <0>;
62
63			#address-cells = <1>;
64			#size-cells = <1>;
65
66			device_type = "cpu";
67
68			mpu: mpu@e000ed90 {
69				compatible = "arm,armv7m-mpu";
70				reg = <0xe000ed90 0x40>;
71			};
72		};
73	};
74
75	soc {
76		sram0: memory@20000000 {
77			compatible = "mmio-sram";
78			reg = <0x20000000 0x40000>;
79		};
80
81		backup0: memory@47000000 {
82			compatible = "mmio-sram";
83			reg = <0x47000000 0x2000>;
84		};
85
86		id: device_id@8061fc {
87			compatible = "atmel,sam0-id";
88			reg =	<0x008061FC 0x4>,
89				<0x00806010 0x4>,
90				<0x00806014 0x4>,
91				<0x00806018 0x4>;
92		};
93
94		mclk: mclk@40000800 {
95			compatible = "atmel,sam0-mclk";
96			reg = <0x40000800 0x400>;
97
98			#clock-cells = <2>;
99		};
100
101		osc32kctrl: osc32kctrl@40001400 {
102			compatible = "atmel,sam0-osc32kctrl";
103			reg = <0x40001400 0x400>;
104			#clock-cells = <0>;
105			#atmel,assigned-clock-cells = <1>;
106		};
107
108		gclk: gclk@40001c00 {
109			compatible = "atmel,sam0-gclk";
110			reg = <0x40001c00 0x400>;
111
112			#clock-cells = <1>;
113			#atmel,assigned-clock-cells = <1>;
114		};
115
116		nvmctrl: nvmctrl@41004000  {
117			compatible = "atmel,sam0-nvmctrl";
118			reg = <0x41004000 0x22>;
119			interrupts = <29 0>, <30 0>;
120
121			#address-cells = <1>;
122			#size-cells = <1>;
123
124			lock-regions = <32>;
125
126			flash0: flash@0 {
127				compatible = "soc-nv-flash";
128
129				write-block-size = <8>;
130			};
131		};
132
133		dmac: dmac@4100a000 {
134			compatible = "atmel,sam0-dmac";
135			reg = <0x4100A000 0x50>;
136			interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>;
137			status = "disabled";
138
139			#dma-cells = <2>;
140		};
141
142		eic: eic@40002800 {
143			compatible = "atmel,sam0-eic";
144			reg = <0x40002800 0x38>;
145			interrupts = <12 0>, <13 0>, <14 0>, <15 0>,
146				     <16 0>, <17 0>, <18 0>, <19 0>,
147				     <20 0>, <21 0>, <22 0>, <23 0>,
148				     <24 0>, <25 0>, <26 0>, <27 0>;
149		};
150
151		pinmux_a: pinmux@41008000 {
152			compatible = "atmel,sam0-pinmux";
153			reg = <0x41008000 0x80>;
154		};
155
156		pinmux_b: pinmux@41008080 {
157			compatible = "atmel,sam0-pinmux";
158			reg = <0x41008080 0x80>;
159		};
160
161		pinmux_c: pinmux@41008100 {
162			compatible = "atmel,sam0-pinmux";
163			reg = <0x41008100 0x80>;
164		};
165
166		pinmux_d: pinmux@41008180 {
167			compatible = "atmel,sam0-pinmux";
168			reg = <0x41008180 0x80>;
169		};
170
171		wdog: watchdog@40002000 {
172			compatible = "atmel,sam0-watchdog";
173			reg = <0x40002000 13>;
174			interrupts = <10 0>;
175		};
176
177		sercom0: sercom@40003000 {
178			compatible = "atmel,sam0-sercom";
179			reg = <0x40003000 0x40>;
180			interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
181			clocks = <&gclk 7>, <&mclk 0x14 12>;
182			clock-names = "GCLK", "MCLK";
183			atmel,assigned-clocks = <&gclk 0>;
184			atmel,assigned-clock-names = "GCLK";
185			status = "disabled";
186		};
187
188		sercom1: sercom@40003400 {
189			compatible = "atmel,sam0-sercom";
190			reg = <0x40003400 0x40>;
191			interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
192			clocks = <&gclk 8>, <&mclk 0x14 13>;
193			clock-names = "GCLK", "MCLK";
194			atmel,assigned-clocks = <&gclk 0>;
195			atmel,assigned-clock-names = "GCLK";
196			status = "disabled";
197		};
198
199		sercom2: sercom@41012000 {
200			compatible = "atmel,sam0-sercom";
201			reg = <0x41012000 0x40>;
202			interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
203			clocks = <&gclk 23>, <&mclk 0x18 9>;
204			clock-names = "GCLK", "MCLK";
205			atmel,assigned-clocks = <&gclk 0>;
206			atmel,assigned-clock-names = "GCLK";
207			status = "disabled";
208		};
209
210		sercom3: sercom@41014000 {
211			compatible = "atmel,sam0-sercom";
212			reg = <0x41014000 0x40>;
213			interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
214			clocks = <&gclk 24>, <&mclk 0x18 10>;
215			clock-names = "GCLK", "MCLK";
216			atmel,assigned-clocks = <&gclk 0>;
217			atmel,assigned-clock-names = "GCLK";
218			status = "disabled";
219		};
220
221		sercom4: sercom@43000000 {
222			compatible = "atmel,sam0-sercom";
223			reg = <0x43000000 0x40>;
224			interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
225			clocks = <&gclk 34>, <&mclk 0x20 0>;
226			clock-names = "GCLK", "MCLK";
227			atmel,assigned-clocks = <&gclk 0>;
228			atmel,assigned-clock-names = "GCLK";
229			status = "disabled";
230		};
231
232		sercom5: sercom@43000400 {
233			compatible = "atmel,sam0-sercom";
234			reg = <0x43000400 0x40>;
235			interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
236			clocks = <&gclk 35>, <&mclk 0x20 1>;
237			clock-names = "GCLK", "MCLK";
238			atmel,assigned-clocks = <&gclk 0>;
239			atmel,assigned-clock-names = "GCLK";
240			status = "disabled";
241		};
242
243		sercom6: sercom@43000800 {
244			compatible = "atmel,sam0-sercom";
245			reg = <0x43000800 0x40>;
246			interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
247			clocks = <&gclk 36>, <&mclk 0x20 2>;
248			clock-names = "GCLK", "MCLK";
249			atmel,assigned-clocks = <&gclk 0>;
250			atmel,assigned-clock-names = "GCLK";
251			status = "disabled";
252		};
253
254		sercom7: sercom@43000c00 {
255			compatible = "atmel,sam0-sercom";
256			reg = <0x43000C00 0x40>;
257			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
258			clocks = <&gclk 37>, <&mclk 0x20 3>;
259			clock-names = "GCLK", "MCLK";
260			atmel,assigned-clocks = <&gclk 0>;
261			atmel,assigned-clock-names = "GCLK";
262			status = "disabled";
263		};
264
265		pinctrl: pinctrl@41008000 {
266			compatible = "atmel,sam0-pinctrl";
267			ranges = <0x41008000 0x41008000 0x200>;
268
269			#address-cells = <1>;
270			#size-cells = <1>;
271
272			porta: gpio@41008000 {
273				compatible = "atmel,sam0-gpio";
274				reg = <0x41008000 0x80>;
275
276				#atmel,pin-cells = <2>;
277				#gpio-cells = <2>;
278
279				gpio-controller;
280			};
281
282			portb: gpio@41008080 {
283				compatible = "atmel,sam0-gpio";
284				reg = <0x41008080 0x80>;
285
286				#atmel,pin-cells = <2>;
287				#gpio-cells = <2>;
288
289				gpio-controller;
290			};
291
292			portc: gpio@41008100 {
293				compatible = "atmel,sam0-gpio";
294				reg = <0x41008100 0x80>;
295
296				#atmel,pin-cells = <2>;
297				#gpio-cells = <2>;
298
299				gpio-controller;
300			};
301
302			portd: gpio@41008180 {
303				compatible = "atmel,sam0-gpio";
304				reg = <0x41008180 0x80>;
305
306				#atmel,pin-cells = <2>;
307				#gpio-cells = <2>;
308
309				gpio-controller;
310			};
311		};
312
313		usb0: usb@41000000 {
314			compatible = "atmel,sam0-usb";
315			reg = <0x41000000 0x1000>;
316			interrupts = <80 0>, <81 0>, <82 0>, <83 0>;
317			status = "disabled";
318
319			num-bidir-endpoints = <8>;
320		};
321
322		trng: random@42002800 {
323			compatible = "atmel,sam-trng";
324			reg = <0x42002800 0x1e>;
325			interrupts = <131 0>;
326		};
327
328		rtc: rtc@40002400 {
329			compatible = "atmel,sam0-rtc";
330			reg = <0x40002400 0x40>;
331			interrupts = <11 0>;
332			clocks = <&osc32kctrl>, <&mclk 0x14 9>;
333			clock-names = "OSC32KCTRL", "MCLK";
334			atmel,assigned-clocks = <&osc32kctrl 0>;
335			atmel,assigned-clock-names = "OSC32KCTRL";
336			status = "disabled";
337
338			alarms-count = <2>;
339			cal-constant = <(8192 * 128)>;
340		};
341
342		adc0: adc@43001c00 {
343			compatible = "atmel,sam0-adc";
344			reg = <0x43001C00 0x4A>;
345			interrupts = <118 0>, <119 0>;
346			interrupt-names = "overrun", "resrdy";
347			clocks = <&gclk 40>, <&mclk 0x20 7>;
348			clock-names = "GCLK", "MCLK";
349			/*
350			 * 16 MHz is ADC max clock, source clock must not exceed 100 MHz.
351			 *	- table 54-8, section 54.6, page 2020
352			 *	- table 54-24, section 54.10.4, page 2031
353			 * 48 MHz GCLK / 4 = 12 MHz
354			 * Generator 2: DFLL48M / 4
355			 */
356			atmel,assigned-clocks = <&gclk 2>;
357			atmel,assigned-clock-names = "GCLK";
358
359			status = "disabled";
360
361			#io-channel-cells = <1>;
362
363			prescaler = <4>;
364			calib-offset = <0>;
365		};
366
367		adc1: adc@43002000 {
368			compatible = "atmel,sam0-adc";
369			reg = <0x43002000 0x4A>;
370			interrupts = <120 0>, <121 0>;
371			interrupt-names = "overrun", "resrdy";
372			clocks = <&gclk 41>, <&mclk 0x20 8>;
373			clock-names = "GCLK", "MCLK";
374			/*
375			 * 16 MHz is ADC max clock, source clock must not exceed 100 MHz.
376			 *	- table 54-8, section 54.6, page 2020
377			 *	- table 54-24, section 54.10.4, page 2031
378			 * 48 MHz GCLK / 4 = 12 MHz
379			 * Generator 2: DFLL48M / 4
380			 */
381			atmel,assigned-clocks = <&gclk 2>;
382			atmel,assigned-clock-names = "GCLK";
383			status = "disabled";
384
385			#io-channel-cells = <1>;
386
387			prescaler = <4>;
388			calib-offset = <14>;
389		};
390
391		tc0: tc@40003800 {
392			compatible = "atmel,sam0-tc32";
393			reg = <0x40003800 0x34>;
394			interrupts = <107 0>;
395			clocks = <&gclk 9>, <&mclk 0x14 14>;
396			clock-names = "GCLK", "MCLK";
397			atmel,assigned-clocks = <&gclk 0>;
398			atmel,assigned-clock-names = "GCLK";
399			status = "disabled";
400		};
401
402		tc2: tc@4101a000 {
403			compatible = "atmel,sam0-tc32";
404			reg = <0x4101A000 0x34>;
405			interrupts = <109 0>;
406			clocks = <&gclk 26>, <&mclk 0x18 13>;
407			clock-names = "GCLK", "MCLK";
408			atmel,assigned-clocks = <&gclk 0>;
409			atmel,assigned-clock-names = "GCLK";
410			status = "disabled";
411		};
412
413		tc4: tc@42001400 {
414			compatible = "atmel,sam0-tc32";
415			reg = <0x42001400 0x34>;
416			interrupts = <111 0>;
417			clocks = <&gclk 30>, <&mclk 0x1c 5>;
418			clock-names = "GCLK", "MCLK";
419			atmel,assigned-clocks = <&gclk 0>;
420			atmel,assigned-clock-names = "GCLK";
421			status = "disabled";
422		};
423
424		tc6: tc@43001400 {
425			compatible = "atmel,sam0-tc32";
426			reg = <0x43001400 0x34>;
427			interrupts = <113 0>;
428			clocks = <&gclk 39>, <&mclk 0x20 5>;
429			clock-names = "GCLK", "MCLK";
430			atmel,assigned-clocks = <&gclk 0>;
431			atmel,assigned-clock-names = "GCLK";
432			status = "disabled";
433		};
434
435		tcc0: tcc@41016000 {
436			compatible = "atmel,sam0-tcc";
437			reg = <0x41016000 0x2000>;
438			interrupts = <85 0>, <86 0>, <87 0>, <88 0>, <89 0>,
439				     <90 0>, <91 0>;
440			clocks = <&gclk 25>, <&mclk 0x18 11>;
441			clock-names = "GCLK", "MCLK";
442			atmel,assigned-clocks = <&gclk 0>;
443			atmel,assigned-clock-names = "GCLK";
444			status = "disabled";
445
446			channels = <6>;
447			counter-size = <24>;
448		};
449
450		tcc1: tcc@41018000 {
451			compatible = "atmel,sam0-tcc";
452			reg = <0x41018000 0x2000>;
453			interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>;
454			clocks = <&gclk 25>, <&mclk 0x18 12>;
455			clock-names = "GCLK", "MCLK";
456			atmel,assigned-clocks = <&gclk 0>;
457			atmel,assigned-clock-names = "GCLK";
458			status = "disabled";
459
460			channels = <4>;
461			counter-size = <24>;
462		};
463
464		tcc2: tcc@42000c00 {
465			compatible = "atmel,sam0-tcc";
466			reg = <0x42000c00 0x400>;
467			interrupts = <97 0>, <98 0>, <99 0>, <100 0>;
468			clocks = <&gclk 29>, <&mclk 0x1c 3>;
469			clock-names = "GCLK", "MCLK";
470			atmel,assigned-clocks = <&gclk 0>;
471			atmel,assigned-clock-names = "GCLK";
472			status = "disabled";
473
474			channels = <3>;
475			counter-size = <16>;
476		};
477
478		tcc3: tcc@42001000 {
479			compatible = "atmel,sam0-tcc";
480			reg = <0x42001000 0x400>;
481			interrupts = <101 0>, <102 0>, <103 0>;
482			clocks = <&gclk 29>, <&mclk 0x1c 4>;
483			clock-names = "GCLK", "MCLK";
484			atmel,assigned-clocks = <&gclk 0>;
485			atmel,assigned-clock-names = "GCLK";
486			status = "disabled";
487
488			channels = <2>;
489			counter-size = <16>;
490		};
491
492		tcc4: tcc@43001000 {
493			compatible = "atmel,sam0-tcc";
494			reg = <0x43001000 0x400>;
495			interrupts = <104 0>, <105 0>, <106 0>;
496			clocks = <&gclk 38>, <&mclk 0x20 4>;
497			clock-names = "GCLK", "MCLK";
498			atmel,assigned-clocks = <&gclk 0>;
499			atmel,assigned-clock-names = "GCLK";
500			status = "disabled";
501
502			channels = <2>;
503			counter-size = <16>;
504		};
505	};
506};
507
508&nvic {
509	arm,num-irq-priority-bits = <3>;
510};
511