1/*
2 * Copyright (c) 2023-2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
8
9/ {
10	soc {
11		pinctrl: pin-controller@40008000 {
12
13			/omit-if-no-ref/ spixr_sdio0_p0_1: spixr_sdio0_p0_1 {
14				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
15			};
16
17			/omit-if-no-ref/ spixf_sdio0_p0_1: spixf_sdio0_p0_1 {
18				pinmux = <MAX32_PINMUX(0, 1, AF2)>;
19			};
20
21			/omit-if-no-ref/ uart2c_tx_p0_1: uart2c_tx_p0_1 {
22				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
23			};
24
25			/omit-if-no-ref/ spixr_sdio2_p0_2: spixr_sdio2_p0_2 {
26				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
27			};
28
29			/omit-if-no-ref/ spixf_sdio2_p0_2: spixf_sdio2_p0_2 {
30				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
31			};
32
33			/omit-if-no-ref/ uart2c_cts_p0_2: uart2c_cts_p0_2 {
34				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
35			};
36
37			/omit-if-no-ref/ spixr_sck_p0_3: spixr_sck_p0_3 {
38				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
39			};
40
41			/omit-if-no-ref/ spixf_sck_p0_3: spixf_sck_p0_3 {
42				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
43			};
44
45			/omit-if-no-ref/ uart2c_rts_p0_3: uart2c_rts_p0_3 {
46				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
47			};
48
49			/omit-if-no-ref/ spixr_sdio3_p0_4: spixr_sdio3_p0_4 {
50				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
51			};
52
53			/omit-if-no-ref/ spixf_sdio3_p0_4: spixf_sdio3_p0_4 {
54				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
55			};
56
57			/omit-if-no-ref/ tmr0c_ioa_p0_4: tmr0c_ioa_p0_4 {
58				pinmux = <MAX32_PINMUX(0, 4, AF3)>;
59			};
60
61			/omit-if-no-ref/ spixr_sdio1_p0_5: spixr_sdio1_p0_5 {
62				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
63			};
64
65			/omit-if-no-ref/ spixf_sdio1_p0_5: spixf_sdio1_p0_5 {
66				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
67			};
68
69			/omit-if-no-ref/ tmr2c_iob_p0_5: tmr2c_iob_p0_5 {
70				pinmux = <MAX32_PINMUX(0, 5, AF3)>;
71			};
72
73			/omit-if-no-ref/ spixr_ss0_p0_6: spixr_ss0_p0_6 {
74				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
75			};
76
77			/omit-if-no-ref/ spixf_ss0_p0_6: spixf_ss0_p0_6 {
78				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
79			};
80
81			/omit-if-no-ref/ uart2c_rx_p0_6: uart2c_rx_p0_6 {
82				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
83			};
84
85			/omit-if-no-ref/ owm_pe_p0_7: owm_pe_p0_7 {
86				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
87			};
88
89			/omit-if-no-ref/ tmr1b_ioa_p0_7: tmr1b_ioa_p0_7 {
90				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
91			};
92
93			/omit-if-no-ref/ owm_io_p0_8: owm_io_p0_8 {
94				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
95			};
96
97			/omit-if-no-ref/ tmr1b_iob_p0_8: tmr1b_iob_p0_8 {
98				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
99			};
100
101			/omit-if-no-ref/ adc_clk_ext_p0_9: adc_clk_ext_p0_9 {
102				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
103			};
104
105			/omit-if-no-ref/ tmr0c_ioan_p0_9: tmr0c_ioan_p0_9 {
106				pinmux = <MAX32_PINMUX(0, 9, AF3)>;
107			};
108
109			/omit-if-no-ref/ adc_trig_a_p0_10: adc_trig_a_p0_10 {
110				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
111			};
112
113			/omit-if-no-ref/ tmr0c_iobn_p0_10: tmr0c_iobn_p0_10 {
114				pinmux = <MAX32_PINMUX(0, 10, AF3)>;
115			};
116
117			/omit-if-no-ref/ i2c1a_sda_p0_11: i2c1a_sda_p0_11 {
118				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
119			};
120
121			/omit-if-no-ref/ tmr1c_ioan_p0_11: tmr1c_ioan_p0_11 {
122				pinmux = <MAX32_PINMUX(0, 11, AF3)>;
123			};
124
125			/omit-if-no-ref/ i2c1a_scl_p0_12: i2c1a_scl_p0_12 {
126				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
127			};
128
129			/omit-if-no-ref/ tmr1c_iobn_p0_12: tmr1c_iobn_p0_12 {
130				pinmux = <MAX32_PINMUX(0, 12, AF3)>;
131			};
132
133			/omit-if-no-ref/ spi3a_ss1_p0_13: spi3a_ss1_p0_13 {
134				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
135			};
136
137			/omit-if-no-ref/ tmr0b_ioa_p0_13: tmr0b_ioa_p0_13 {
138				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
139			};
140
141			/omit-if-no-ref/ i2c2c_sda_p0_13: i2c2c_sda_p0_13 {
142				pinmux = <MAX32_PINMUX(0, 13, AF3)>;
143			};
144
145			/omit-if-no-ref/ spi3a_ss2_p0_14: spi3a_ss2_p0_14 {
146				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
147			};
148
149			/omit-if-no-ref/ tmr0b_iob_p0_14: tmr0b_iob_p0_14 {
150				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
151			};
152
153			/omit-if-no-ref/ i2c2c_scl_p0_14: i2c2c_scl_p0_14 {
154				pinmux = <MAX32_PINMUX(0, 14, AF3)>;
155			};
156
157			/omit-if-no-ref/ spi3a_sdio3_p0_15: spi3a_sdio3_p0_15 {
158				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
159			};
160
161			/omit-if-no-ref/ tmr1c_ioa_p0_15: tmr1c_ioa_p0_15 {
162				pinmux = <MAX32_PINMUX(0, 15, AF3)>;
163			};
164
165			/omit-if-no-ref/ spi3a_sck_p0_16: spi3a_sck_p0_16 {
166				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
167			};
168
169			/omit-if-no-ref/ spi3a_sdio2_p0_17: spi3a_sdio2_p0_17 {
170				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
171			};
172
173			/omit-if-no-ref/ tmr1c_iob_p0_17: tmr1c_iob_p0_17 {
174				pinmux = <MAX32_PINMUX(0, 17, AF3)>;
175			};
176
177			/omit-if-no-ref/ spi3a_ss0_p0_19: spi3a_ss0_p0_19 {
178				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
179			};
180
181			/omit-if-no-ref/ rv_tck_p0_19: rv_tck_p0_19 {
182				pinmux = <MAX32_PINMUX(0, 19, AF2)>;
183			};
184
185			/omit-if-no-ref/ spi3a_miso_p0_20: spi3a_miso_p0_20 {
186				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
187			};
188
189			/omit-if-no-ref/ rv_tms_p0_20: rv_tms_p0_20 {
190				pinmux = <MAX32_PINMUX(0, 20, AF2)>;
191			};
192
193			/omit-if-no-ref/ spi3a_mosi_p0_21: spi3a_mosi_p0_21 {
194				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
195			};
196
197			/omit-if-no-ref/ rv_tdi_p0_21: rv_tdi_p0_21 {
198				pinmux = <MAX32_PINMUX(0, 21, AF2)>;
199			};
200
201			/omit-if-no-ref/ spi0a_ss0_p0_22: spi0a_ss0_p0_22 {
202				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
203			};
204
205			/omit-if-no-ref/ rv_tdo_p0_22: rv_tdo_p0_22 {
206				pinmux = <MAX32_PINMUX(0, 22, AF2)>;
207			};
208
209			/omit-if-no-ref/ pt15_p0_23: pt15_p0_23 {
210				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
211			};
212
213			/omit-if-no-ref/ i2s0b_clkext_p0_23: i2s0b_clkext_p0_23 {
214				pinmux = <MAX32_PINMUX(0, 23, AF2)>;
215			};
216
217			/omit-if-no-ref/ rxev0_p0_24: rxev0_p0_24 {
218				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
219			};
220
221			/omit-if-no-ref/ i2s0b_sck_p0_24: i2s0b_sck_p0_24 {
222				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
223			};
224
225			/omit-if-no-ref/ txevo_p0_25: txevo_p0_25 {
226				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
227			};
228
229			/omit-if-no-ref/ i2s0b_sdi_p0_25: i2s0b_sdi_p0_25 {
230				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
231			};
232
233			/omit-if-no-ref/ i2s0b_sdo_p0_26: i2s0b_sdo_p0_26 {
234				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
235			};
236
237			/omit-if-no-ref/ erfo_clk_out_p0_27: erfo_clk_out_p0_27 {
238				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
239			};
240
241			/omit-if-no-ref/ i2s0b_ws_p0_27: i2s0b_ws_p0_27 {
242				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
243			};
244
245			/omit-if-no-ref/ i2c0a_sda_p0_30: i2c0a_sda_p0_30 {
246				pinmux = <MAX32_PINMUX(0, 30, AF1)>;
247			};
248
249			/omit-if-no-ref/ i2c0a_scl_p0_31: i2c0a_scl_p0_31 {
250				pinmux = <MAX32_PINMUX(0, 31, AF1)>;
251			};
252
253			/omit-if-no-ref/ spi4a_ss0_p1_0: spi4a_ss0_p1_0 {
254				pinmux = <MAX32_PINMUX(1, 0, AF1)>;
255			};
256
257			/omit-if-no-ref/ adc_trig_b_p1_0: adc_trig_b_p1_0 {
258				pinmux = <MAX32_PINMUX(1, 0, AF2)>;
259			};
260
261			/omit-if-no-ref/ spi4a_mosi_p1_1: spi4a_mosi_p1_1 {
262				pinmux = <MAX32_PINMUX(1, 1, AF1)>;
263			};
264
265			/omit-if-no-ref/ spi4a_miso_p1_2: spi4a_miso_p1_2 {
266				pinmux = <MAX32_PINMUX(1, 2, AF1)>;
267			};
268
269			/omit-if-no-ref/ spi4a_sck_p1_3: spi4a_sck_p1_3 {
270				pinmux = <MAX32_PINMUX(1, 3, AF1)>;
271			};
272
273			/omit-if-no-ref/ spi4a_sdio2_p1_4: spi4a_sdio2_p1_4 {
274				pinmux = <MAX32_PINMUX(1, 4, AF1)>;
275			};
276
277			/omit-if-no-ref/ tmr2b_ioa_p1_4: tmr2b_ioa_p1_4 {
278				pinmux = <MAX32_PINMUX(1, 4, AF2)>;
279			};
280
281			/omit-if-no-ref/ spi4a_sdio3_p1_5: spi4a_sdio3_p1_5 {
282				pinmux = <MAX32_PINMUX(1, 5, AF1)>;
283			};
284
285			/omit-if-no-ref/ tmr2b_iob_p1_5: tmr2b_iob_p1_5 {
286				pinmux = <MAX32_PINMUX(1, 5, AF2)>;
287			};
288
289			/omit-if-no-ref/ spi4a_ss1_p1_6: spi4a_ss1_p1_6 {
290				pinmux = <MAX32_PINMUX(1, 6, AF1)>;
291			};
292
293			/omit-if-no-ref/ pt0_p1_6: pt0_p1_6 {
294				pinmux = <MAX32_PINMUX(1, 6, AF2)>;
295			};
296
297			/omit-if-no-ref/ uart2a_cts_p1_7: uart2a_cts_p1_7 {
298				pinmux = <MAX32_PINMUX(1, 7, AF1)>;
299			};
300
301			/omit-if-no-ref/ pt1_p1_7: pt1_p1_7 {
302				pinmux = <MAX32_PINMUX(1, 7, AF2)>;
303			};
304
305			/omit-if-no-ref/ i2c2c_sda_p1_7: i2c2c_sda_p1_7 {
306				pinmux = <MAX32_PINMUX(1, 7, AF3)>;
307			};
308
309			/omit-if-no-ref/ uart2a_rts_p1_8: uart2a_rts_p1_8 {
310				pinmux = <MAX32_PINMUX(1, 8, AF1)>;
311			};
312
313			/omit-if-no-ref/ pt2_p1_8: pt2_p1_8 {
314				pinmux = <MAX32_PINMUX(1, 8, AF2)>;
315			};
316
317			/omit-if-no-ref/ i2c2c_scl_p1_8: i2c2c_scl_p1_8 {
318				pinmux = <MAX32_PINMUX(1, 8, AF3)>;
319			};
320
321			/omit-if-no-ref/ uart2a_rx_p1_9: uart2a_rx_p1_9 {
322				pinmux = <MAX32_PINMUX(1, 9, AF1)>;
323			};
324
325			/omit-if-no-ref/ pt3_p1_9: pt3_p1_9 {
326				pinmux = <MAX32_PINMUX(1, 9, AF2)>;
327			};
328
329			/omit-if-no-ref/ uart2a_tx_p1_10: uart2a_tx_p1_10 {
330				pinmux = <MAX32_PINMUX(1, 10, AF1)>;
331			};
332
333			/omit-if-no-ref/ pt4_p1_10: pt4_p1_10 {
334				pinmux = <MAX32_PINMUX(1, 10, AF2)>;
335			};
336
337			/omit-if-no-ref/ spi4a_ss2_p1_11: spi4a_ss2_p1_11 {
338				pinmux = <MAX32_PINMUX(1, 11, AF1)>;
339			};
340
341			/omit-if-no-ref/ hyp_cs0n_p1_11: hyp_cs0n_p1_11 {
342				pinmux = <MAX32_PINMUX(1, 11, AF3)>;
343			};
344
345			/omit-if-no-ref/ pt5_p1_12: pt5_p1_12 {
346				pinmux = <MAX32_PINMUX(1, 12, AF1)>;
347			};
348
349			/omit-if-no-ref/ hyp_d0_p1_12: hyp_d0_p1_12 {
350				pinmux = <MAX32_PINMUX(1, 12, AF2)>;
351			};
352
353			/omit-if-no-ref/ tmr3a_ioa_p1_13: tmr3a_ioa_p1_13 {
354				pinmux = <MAX32_PINMUX(1, 13, AF1)>;
355			};
356
357			/omit-if-no-ref/ hyp_d4_p1_13: hyp_d4_p1_13 {
358				pinmux = <MAX32_PINMUX(1, 13, AF3)>;
359			};
360
361			/omit-if-no-ref/ tmr3a_iob_p1_14: tmr3a_iob_p1_14 {
362				pinmux = <MAX32_PINMUX(1, 14, AF1)>;
363			};
364
365			/omit-if-no-ref/ hyp_rwds_p1_14: hyp_rwds_p1_14 {
366				pinmux = <MAX32_PINMUX(1, 14, AF3)>;
367			};
368
369			/omit-if-no-ref/ hyp_d1_p1_15: hyp_d1_p1_15 {
370				pinmux = <MAX32_PINMUX(1, 15, AF3)>;
371			};
372
373			/omit-if-no-ref/ hyp_d5_p1_16: hyp_d5_p1_16 {
374				pinmux = <MAX32_PINMUX(1, 16, AF3)>;
375			};
376
377			/omit-if-no-ref/ pt9_p1_17: pt9_p1_17 {
378				pinmux = <MAX32_PINMUX(1, 17, AF1)>;
379			};
380
381			/omit-if-no-ref/ hyp_cs1n_p1_17: hyp_cs1n_p1_17 {
382				pinmux = <MAX32_PINMUX(1, 17, AF3)>;
383			};
384
385			/omit-if-no-ref/ pt6_p1_18: pt6_p1_18 {
386				pinmux = <MAX32_PINMUX(1, 18, AF2)>;
387			};
388
389			/omit-if-no-ref/ hyp_d6_p1_18: hyp_d6_p1_18 {
390				pinmux = <MAX32_PINMUX(1, 18, AF3)>;
391			};
392
393			/omit-if-no-ref/ pt7_p1_19: pt7_p1_19 {
394				pinmux = <MAX32_PINMUX(1, 19, AF2)>;
395			};
396
397			/omit-if-no-ref/ hyp_d2_p1_19: hyp_d2_p1_19 {
398				pinmux = <MAX32_PINMUX(1, 19, AF3)>;
399			};
400
401			/omit-if-no-ref/ hyp_d3_p1_20: hyp_d3_p1_20 {
402				pinmux = <MAX32_PINMUX(1, 20, AF3)>;
403			};
404
405			/omit-if-no-ref/ pt8_p1_21: pt8_p1_21 {
406				pinmux = <MAX32_PINMUX(1, 21, AF2)>;
407			};
408
409			/omit-if-no-ref/ hyp_d7_p1_21: hyp_d7_p1_21 {
410				pinmux = <MAX32_PINMUX(1, 21, AF3)>;
411			};
412
413			/omit-if-no-ref/ spi1a_ss0_p1_23: spi1a_ss0_p1_23 {
414				pinmux = <MAX32_PINMUX(1, 23, AF1)>;
415			};
416
417			/omit-if-no-ref/ spi1a_ss2_p1_24: spi1a_ss2_p1_24 {
418				pinmux = <MAX32_PINMUX(1, 24, AF1)>;
419			};
420
421			/omit-if-no-ref/ can0b_rx_p1_24: can0b_rx_p1_24 {
422				pinmux = <MAX32_PINMUX(1, 24, AF2)>;
423			};
424
425			/omit-if-no-ref/ spi1a_ss1_p1_25: spi1a_ss1_p1_25 {
426				pinmux = <MAX32_PINMUX(1, 25, AF1)>;
427			};
428
429			/omit-if-no-ref/ can0b_tx_p1_25: can0b_tx_p1_25 {
430				pinmux = <MAX32_PINMUX(1, 25, AF2)>;
431			};
432
433			/omit-if-no-ref/ spi1a_sck_p1_26: spi1a_sck_p1_26 {
434				pinmux = <MAX32_PINMUX(1, 26, AF1)>;
435			};
436
437			/omit-if-no-ref/ spi2a_ss2_p1_27: spi2a_ss2_p1_27 {
438				pinmux = <MAX32_PINMUX(1, 27, AF1)>;
439			};
440
441			/omit-if-no-ref/ spi1a_miso_p1_28: spi1a_miso_p1_28 {
442				pinmux = <MAX32_PINMUX(1, 28, AF1)>;
443			};
444
445			/omit-if-no-ref/ can1b_rx_p1_28: can1b_rx_p1_28 {
446				pinmux = <MAX32_PINMUX(1, 28, AF2)>;
447			};
448
449			/omit-if-no-ref/ spi1a_mosi_p1_29: spi1a_mosi_p1_29 {
450				pinmux = <MAX32_PINMUX(1, 29, AF1)>;
451			};
452
453			/omit-if-no-ref/ can1b_tx_p1_29: can1b_tx_p1_29 {
454				pinmux = <MAX32_PINMUX(1, 29, AF2)>;
455			};
456
457			/omit-if-no-ref/ owm_pe_p1_30: owm_pe_p1_30 {
458				pinmux = <MAX32_PINMUX(1, 30, AF1)>;
459			};
460
461			/omit-if-no-ref/ spi1b_sdio2_p1_30: spi1b_sdio2_p1_30 {
462				pinmux = <MAX32_PINMUX(1, 30, AF2)>;
463			};
464
465			/omit-if-no-ref/ owm_io_p1_31: owm_io_p1_31 {
466				pinmux = <MAX32_PINMUX(1, 31, AF1)>;
467			};
468
469			/omit-if-no-ref/ spi1b_sdio3_p1_31: spi1b_sdio3_p1_31 {
470				pinmux = <MAX32_PINMUX(1, 31, AF2)>;
471			};
472
473			/omit-if-no-ref/ spi2a_ss1_p2_1: spi2a_ss1_p2_1 {
474				pinmux = <MAX32_PINMUX(2, 1, AF1)>;
475			};
476
477			/omit-if-no-ref/ pt10_p2_1: pt10_p2_1 {
478				pinmux = <MAX32_PINMUX(2, 1, AF2)>;
479			};
480
481			/omit-if-no-ref/ spi2a_sck_p2_2: spi2a_sck_p2_2 {
482				pinmux = <MAX32_PINMUX(2, 2, AF1)>;
483			};
484
485			/omit-if-no-ref/ spi2a_miso_p2_3: spi2a_miso_p2_3 {
486				pinmux = <MAX32_PINMUX(2, 3, AF1)>;
487			};
488
489			/omit-if-no-ref/ spi2a_mosi_p2_4: spi2a_mosi_p2_4 {
490				pinmux = <MAX32_PINMUX(2, 4, AF1)>;
491			};
492
493			/omit-if-no-ref/ spi2a_ss0_p2_5: spi2a_ss0_p2_5 {
494				pinmux = <MAX32_PINMUX(2, 5, AF1)>;
495			};
496
497			/omit-if-no-ref/ pt11_p2_5: pt11_p2_5 {
498				pinmux = <MAX32_PINMUX(2, 5, AF2)>;
499			};
500
501			/omit-if-no-ref/ spi2b_sdio2_p2_6: spi2b_sdio2_p2_6 {
502				pinmux = <MAX32_PINMUX(2, 6, AF2)>;
503			};
504
505			/omit-if-no-ref/ i2c0a_sda_p2_7: i2c0a_sda_p2_7 {
506				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
507			};
508
509			/omit-if-no-ref/ spi2b_sdio3_p2_7: spi2b_sdio3_p2_7 {
510				pinmux = <MAX32_PINMUX(2, 7, AF2)>;
511			};
512
513			/omit-if-no-ref/ i2c0a_scl_p2_8: i2c0a_scl_p2_8 {
514				pinmux = <MAX32_PINMUX(2, 8, AF1)>;
515			};
516
517			/omit-if-no-ref/ uart0a_cts_p2_9: uart0a_cts_p2_9 {
518				pinmux = <MAX32_PINMUX(2, 9, AF1)>;
519			};
520
521			/omit-if-no-ref/ pt12_p2_9: pt12_p2_9 {
522				pinmux = <MAX32_PINMUX(2, 9, AF2)>;
523			};
524
525			/omit-if-no-ref/ uart0a_rts_p2_10: uart0a_rts_p2_10 {
526				pinmux = <MAX32_PINMUX(2, 10, AF1)>;
527			};
528
529			/omit-if-no-ref/ pt14_p2_10: pt14_p2_10 {
530				pinmux = <MAX32_PINMUX(2, 10, AF2)>;
531			};
532
533			/omit-if-no-ref/ uart0a_rx_p2_11: uart0a_rx_p2_11 {
534				pinmux = <MAX32_PINMUX(2, 11, AF1)>;
535			};
536
537			/omit-if-no-ref/ pt13_p2_11: pt13_p2_11 {
538				pinmux = <MAX32_PINMUX(2, 11, AF2)>;
539			};
540
541			/omit-if-no-ref/ uart0a_tx_p2_12: uart0a_tx_p2_12 {
542				pinmux = <MAX32_PINMUX(2, 12, AF1)>;
543			};
544
545			/omit-if-no-ref/ pt15_p2_12: pt15_p2_12 {
546				pinmux = <MAX32_PINMUX(2, 12, AF2)>;
547			};
548
549			/omit-if-no-ref/ uart1a_cts_p2_13: uart1a_cts_p2_13 {
550				pinmux = <MAX32_PINMUX(2, 13, AF1)>;
551			};
552
553			/omit-if-no-ref/ uart1a_rx_p2_14: uart1a_rx_p2_14 {
554				pinmux = <MAX32_PINMUX(2, 14, AF1)>;
555			};
556
557			/omit-if-no-ref/ uart1a_rts_p2_15: uart1a_rts_p2_15 {
558				pinmux = <MAX32_PINMUX(2, 15, AF1)>;
559			};
560
561			/omit-if-no-ref/ adc_hw_trig_c_p2_15: adc_hw_trig_c_p2_15 {
562				pinmux = <MAX32_PINMUX(2, 15, AF2)>;
563			};
564
565			/omit-if-no-ref/ uart1a_tx_p2_16: uart1a_tx_p2_16 {
566				pinmux = <MAX32_PINMUX(2, 16, AF1)>;
567			};
568
569			/omit-if-no-ref/ i2c1a_sda_p2_17: i2c1a_sda_p2_17 {
570				pinmux = <MAX32_PINMUX(2, 17, AF1)>;
571			};
572
573			/omit-if-no-ref/ ble_ant_ctrl1_p2_17: ble_ant_ctrl1_p2_17 {
574				pinmux = <MAX32_PINMUX(2, 17, AF2)>;
575			};
576
577			/omit-if-no-ref/ i2c1a_scl_p2_18: i2c1a_scl_p2_18 {
578				pinmux = <MAX32_PINMUX(2, 18, AF1)>;
579			};
580
581			/omit-if-no-ref/ ble_ant_ctrl0_p2_18: ble_ant_ctrl0_p2_18 {
582				pinmux = <MAX32_PINMUX(2, 18, AF2)>;
583			};
584
585			/omit-if-no-ref/ pt5_p2_20: pt5_p2_20 {
586				pinmux = <MAX32_PINMUX(2, 20, AF1)>;
587			};
588
589			/omit-if-no-ref/ ble_ant_ctrl2_p2_20: ble_ant_ctrl2_p2_20 {
590				pinmux = <MAX32_PINMUX(2, 20, AF2)>;
591			};
592
593			/omit-if-no-ref/ tmr2c_ioa_p2_20: tmr2c_ioa_p2_20 {
594				pinmux = <MAX32_PINMUX(2, 20, AF3)>;
595			};
596
597			/omit-if-no-ref/ pt7_p2_21: pt7_p2_21 {
598				pinmux = <MAX32_PINMUX(2, 21, AF1)>;
599			};
600
601			/omit-if-no-ref/ ble_ant_ctrl3_p2_21: ble_ant_ctrl3_p2_21 {
602				pinmux = <MAX32_PINMUX(2, 21, AF2)>;
603			};
604
605			/omit-if-no-ref/ tmr2c_iob_p2_21: tmr2c_iob_p2_21 {
606				pinmux = <MAX32_PINMUX(2, 21, AF3)>;
607			};
608
609			/omit-if-no-ref/ pt8_p2_22: pt8_p2_22 {
610				pinmux = <MAX32_PINMUX(2, 22, AF1)>;
611			};
612
613			/omit-if-no-ref/ can0b_rx_p2_22: can0b_rx_p2_22 {
614				pinmux = <MAX32_PINMUX(2, 22, AF2)>;
615			};
616
617			/omit-if-no-ref/ pt6_p2_23: pt6_p2_23 {
618				pinmux = <MAX32_PINMUX(2, 23, AF1)>;
619			};
620
621			/omit-if-no-ref/ can0b_tx_p2_23: can0b_tx_p2_23 {
622				pinmux = <MAX32_PINMUX(2, 23, AF2)>;
623			};
624
625			/omit-if-no-ref/ pt10_p2_24: pt10_p2_24 {
626				pinmux = <MAX32_PINMUX(2, 24, AF1)>;
627			};
628
629			/omit-if-no-ref/ can1b_rx_p2_24: can1b_rx_p2_24 {
630				pinmux = <MAX32_PINMUX(2, 24, AF2)>;
631			};
632
633			/omit-if-no-ref/ pt11_p2_25: pt11_p2_25 {
634				pinmux = <MAX32_PINMUX(2, 25, AF1)>;
635			};
636
637			/omit-if-no-ref/ can1b_tx_p2_25: can1b_tx_p2_25 {
638				pinmux = <MAX32_PINMUX(2, 25, AF2)>;
639			};
640
641			/omit-if-no-ref/ pt12_p2_26: pt12_p2_26 {
642				pinmux = <MAX32_PINMUX(2, 26, AF1)>;
643			};
644
645			/omit-if-no-ref/ spi0b_ss1_p2_26: spi0b_ss1_p2_26 {
646				pinmux = <MAX32_PINMUX(2, 26, AF2)>;
647			};
648
649			/omit-if-no-ref/ i2s0c_ws_p2_26: i2s0c_ws_p2_26 {
650				pinmux = <MAX32_PINMUX(2, 26, AF3)>;
651			};
652
653			/omit-if-no-ref/ pt13_p2_27: pt13_p2_27 {
654				pinmux = <MAX32_PINMUX(2, 27, AF1)>;
655			};
656
657			/omit-if-no-ref/ spi0b_miso_p2_27: spi0b_miso_p2_27 {
658				pinmux = <MAX32_PINMUX(2, 27, AF2)>;
659			};
660
661			/omit-if-no-ref/ i2s0c_sdi_p2_27: i2s0c_sdi_p2_27 {
662				pinmux = <MAX32_PINMUX(2, 27, AF3)>;
663			};
664
665			/omit-if-no-ref/ pt14_p2_28: pt14_p2_28 {
666				pinmux = <MAX32_PINMUX(2, 28, AF1)>;
667			};
668
669			/omit-if-no-ref/ spi0b_mosi_p2_28: spi0b_mosi_p2_28 {
670				pinmux = <MAX32_PINMUX(2, 28, AF2)>;
671			};
672
673			/omit-if-no-ref/ i2s0c_sdo_p2_28: i2s0c_sdo_p2_28 {
674				pinmux = <MAX32_PINMUX(2, 28, AF3)>;
675			};
676
677			/omit-if-no-ref/ pt0_p2_29: pt0_p2_29 {
678				pinmux = <MAX32_PINMUX(2, 29, AF1)>;
679			};
680
681			/omit-if-no-ref/ spi0b_sck_p2_29: spi0b_sck_p2_29 {
682				pinmux = <MAX32_PINMUX(2, 29, AF2)>;
683			};
684
685			/omit-if-no-ref/ i2s0c_sck_p2_29: i2s0c_sck_p2_29 {
686				pinmux = <MAX32_PINMUX(2, 29, AF3)>;
687			};
688
689			/omit-if-no-ref/ pt1_p2_30: pt1_p2_30 {
690				pinmux = <MAX32_PINMUX(2, 30, AF1)>;
691			};
692
693			/omit-if-no-ref/ spi0b_sdio2_p2_30: spi0b_sdio2_p2_30 {
694				pinmux = <MAX32_PINMUX(2, 30, AF2)>;
695			};
696
697			/omit-if-no-ref/ tmr3c_ioa_p2_30: tmr3c_ioa_p2_30 {
698				pinmux = <MAX32_PINMUX(2, 30, AF3)>;
699			};
700
701			/omit-if-no-ref/ pt2_p2_31: pt2_p2_31 {
702				pinmux = <MAX32_PINMUX(2, 31, AF1)>;
703			};
704
705			/omit-if-no-ref/ spi0b_sdio3_p2_31: spi0b_sdio3_p2_31 {
706				pinmux = <MAX32_PINMUX(2, 31, AF2)>;
707			};
708
709			/omit-if-no-ref/ tmr3c_iob_p2_31: tmr3c_iob_p2_31 {
710				pinmux = <MAX32_PINMUX(2, 31, AF3)>;
711			};
712
713			/omit-if-no-ref/ ain0_p3_0: ain0_p3_0 {
714				pinmux = <MAX32_PINMUX(3, 0, AF1)>;
715			};
716
717			/omit-if-no-ref/ lpuart0b_rx_p3_0: lpuart0b_rx_p3_0 {
718				pinmux = <MAX32_PINMUX(3, 0, AF2)>;
719			};
720
721			/omit-if-no-ref/ ain1_p3_1: ain1_p3_1 {
722				pinmux = <MAX32_PINMUX(3, 1, AF1)>;
723			};
724
725			/omit-if-no-ref/ lpuart0b_tx_p3_1: lpuart0b_tx_p3_1 {
726				pinmux = <MAX32_PINMUX(3, 1, AF2)>;
727			};
728
729			/omit-if-no-ref/ ain2_p3_2: ain2_p3_2 {
730				pinmux = <MAX32_PINMUX(3, 2, AF1)>;
731			};
732
733			/omit-if-no-ref/ lpuart0b_cts_p3_2: lpuart0b_cts_p3_2 {
734				pinmux = <MAX32_PINMUX(3, 2, AF2)>;
735			};
736
737			/omit-if-no-ref/ ain3_p3_3: ain3_p3_3 {
738				pinmux = <MAX32_PINMUX(3, 3, AF1)>;
739			};
740
741			/omit-if-no-ref/ lpuart0b_rts_p3_3: lpuart0b_rts_p3_3 {
742				pinmux = <MAX32_PINMUX(3, 3, AF2)>;
743			};
744
745			/omit-if-no-ref/ ain4_p3_4: ain4_p3_4 {
746				pinmux = <MAX32_PINMUX(3, 4, AF1)>;
747			};
748
749			/omit-if-no-ref/ lptmr0b_ioa_p3_4: lptmr0b_ioa_p3_4 {
750				pinmux = <MAX32_PINMUX(3, 4, AF2)>;
751			};
752
753			/omit-if-no-ref/ ain5_p3_5: ain5_p3_5 {
754				pinmux = <MAX32_PINMUX(3, 5, AF1)>;
755			};
756
757			/omit-if-no-ref/ ain6_p3_6: ain6_p3_6 {
758				pinmux = <MAX32_PINMUX(3, 6, AF1)>;
759			};
760
761			/omit-if-no-ref/ ain7_p3_7: ain7_p3_7 {
762				pinmux = <MAX32_PINMUX(3, 7, AF1)>;
763			};
764
765			/omit-if-no-ref/ lptmr1b_ioa_p3_7: lptmr1b_ioa_p3_7 {
766				pinmux = <MAX32_PINMUX(3, 7, AF2)>;
767			};
768
769		};
770	};
771};
772