1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
8
9/ {
10	soc {
11		pinctrl: pin-controller@40008000 {
12
13			/omit-if-no-ref/ uart0a_rx_p0_0: uart0a_rx_p0_0 {
14				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
15			};
16
17			/omit-if-no-ref/ uart0a_tx_p0_1: uart0a_tx_p0_1 {
18				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
19			};
20
21			/omit-if-no-ref/ tmr0a_ioa_p0_2: tmr0a_ioa_p0_2 {
22				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
23			};
24
25			/omit-if-no-ref/ uart0b_cts_p0_2: uart0b_cts_p0_2 {
26				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
27			};
28
29			/omit-if-no-ref/ ext_clk_p0_3: ext_clk_p0_3 {
30				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
31			};
32
33			/omit-if-no-ref/ spi0a_ss0_p0_4: spi0a_ss0_p0_4 {
34				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
35			};
36
37			/omit-if-no-ref/ tmr0b_ioan_p0_4: tmr0b_ioan_p0_4 {
38				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
39			};
40
41			/omit-if-no-ref/ spi0a_mosi_p0_5: spi0a_mosi_p0_5 {
42				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
43			};
44
45			/omit-if-no-ref/ tmr0b_iobn_p0_5: tmr0b_iobn_p0_5 {
46				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
47			};
48
49			/omit-if-no-ref/ spi0a_miso_p0_6: spi0a_miso_p0_6 {
50				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
51			};
52
53			/omit-if-no-ref/ owm_io_p0_6: owm_io_p0_6 {
54				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
55			};
56
57			/omit-if-no-ref/ spi0a_sck_p0_7: spi0a_sck_p0_7 {
58				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
59			};
60
61			/omit-if-no-ref/ owm_pe_p0_7: owm_pe_p0_7 {
62				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
63			};
64
65			/omit-if-no-ref/ spi0a_sdio2_p0_8: spi0a_sdio2_p0_8 {
66				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
67			};
68
69			/omit-if-no-ref/ tmr0b_ioa_p0_8: tmr0b_ioa_p0_8 {
70				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
71			};
72
73			/omit-if-no-ref/ spi0a_sdio3_p0_9: spi0a_sdio3_p0_9 {
74				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
75			};
76
77			/omit-if-no-ref/ tmr0b_iob_p0_9: tmr0b_iob_p0_9 {
78				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
79			};
80
81			/omit-if-no-ref/ i2c0a_scl_p0_10: i2c0a_scl_p0_10 {
82				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
83			};
84
85			/omit-if-no-ref/ spi0b_ss2_p0_10: spi0b_ss2_p0_10 {
86				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
87			};
88
89			/omit-if-no-ref/ i2c0a_sda_p0_11: i2c0a_sda_p0_11 {
90				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
91			};
92
93			/omit-if-no-ref/ spi0b_ss1_p0_11: spi0b_ss1_p0_11 {
94				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
95			};
96
97			/omit-if-no-ref/ uart1a_rx_p0_12: uart1a_rx_p0_12 {
98				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
99			};
100
101			/omit-if-no-ref/ tmr1b_ioa_p0_12: tmr1b_ioa_p0_12 {
102				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
103			};
104
105			/omit-if-no-ref/ uart1a_tx_p0_13: uart1a_tx_p0_13 {
106				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
107			};
108
109			/omit-if-no-ref/ tmr1b_iobn_p0_13: tmr1b_iobn_p0_13 {
110				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
111			};
112
113			/omit-if-no-ref/ tmr1a_ioa_p0_14: tmr1a_ioa_p0_14 {
114				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
115			};
116
117			/omit-if-no-ref/ uart1b_cts_p0_14: uart1b_cts_p0_14 {
118				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
119			};
120
121			/omit-if-no-ref/ tmr1a_iob_p0_15: tmr1a_iob_p0_15 {
122				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
123			};
124
125			/omit-if-no-ref/ uart1b_rts_p0_15: uart1b_rts_p0_15 {
126				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
127			};
128
129			/omit-if-no-ref/ i2c1a_scl_p0_16: i2c1a_scl_p0_16 {
130				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
131			};
132
133			/omit-if-no-ref/ pt2_p0_16: pt2_p0_16 {
134				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
135			};
136
137			/omit-if-no-ref/ i2c1a_sda_p0_17: i2c1a_sda_p0_17 {
138				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
139			};
140
141			/omit-if-no-ref/ pt3_p0_17: pt3_p0_17 {
142				pinmux = <MAX32_PINMUX(0, 17, AF2)>;
143			};
144
145			/omit-if-no-ref/ spi1a_sdio2_p0_24: spi1a_sdio2_p0_24 {
146				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
147			};
148
149			/omit-if-no-ref/ tmr2b_ioa_p0_24: tmr2b_ioa_p0_24 {
150				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
151			};
152
153			/omit-if-no-ref/ adc0_rdy_p0_24: adc0_rdy_p0_24 {
154				pinmux = <MAX32_PINMUX(0, 24, AF3)>;
155			};
156
157			/omit-if-no-ref/ spi1a_sdio3_p0_25: spi1a_sdio3_p0_25 {
158				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
159			};
160
161			/omit-if-no-ref/ tmr2b_iob_p0_25: tmr2b_iob_p0_25 {
162				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
163			};
164
165			/omit-if-no-ref/ adc1_rdy_p0_25: adc1_rdy_p0_25 {
166				pinmux = <MAX32_PINMUX(0, 25, AF3)>;
167			};
168
169			/omit-if-no-ref/ tmr2a_ioa_p0_26: tmr2a_ioa_p0_26 {
170				pinmux = <MAX32_PINMUX(0, 26, AF1)>;
171			};
172
173			/omit-if-no-ref/ spi1b_ss1_p0_26: spi1b_ss1_p0_26 {
174				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
175			};
176
177			/omit-if-no-ref/ tmr2a_iob_p0_27: tmr2a_iob_p0_27 {
178				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
179			};
180
181			/omit-if-no-ref/ spi1b_ss2_p0_27: spi1b_ss2_p0_27 {
182				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
183			};
184
185			/omit-if-no-ref/ swdio_p0_28: swdio_p0_28 {
186				pinmux = <MAX32_PINMUX(0, 28, AF1)>;
187			};
188
189			/omit-if-no-ref/ swclk_p0_29: swclk_p0_29 {
190				pinmux = <MAX32_PINMUX(0, 29, AF1)>;
191			};
192
193			/omit-if-no-ref/ uart2a_rx_p1_0: uart2a_rx_p1_0 {
194				pinmux = <MAX32_PINMUX(1, 0, AF1)>;
195			};
196
197			/omit-if-no-ref/ rv_tck_p1_0: rv_tck_p1_0 {
198				pinmux = <MAX32_PINMUX(1, 0, AF2)>;
199			};
200
201			/omit-if-no-ref/ uart2a_tx_p1_1: uart2a_tx_p1_1 {
202				pinmux = <MAX32_PINMUX(1, 1, AF1)>;
203			};
204
205			/omit-if-no-ref/ rv_tms_p1_1: rv_tms_p1_1 {
206				pinmux = <MAX32_PINMUX(1, 1, AF2)>;
207			};
208
209			/omit-if-no-ref/ i2s0a_sck_p1_2: i2s0a_sck_p1_2 {
210				pinmux = <MAX32_PINMUX(1, 2, AF1)>;
211			};
212
213			/omit-if-no-ref/ rv_tdi_p1_2: rv_tdi_p1_2 {
214				pinmux = <MAX32_PINMUX(1, 2, AF2)>;
215			};
216
217			/omit-if-no-ref/ i2s0a_lrclk_p1_3: i2s0a_lrclk_p1_3 {
218				pinmux = <MAX32_PINMUX(1, 3, AF1)>;
219			};
220
221			/omit-if-no-ref/ rv_tdo_p1_3: rv_tdo_p1_3 {
222				pinmux = <MAX32_PINMUX(1, 3, AF2)>;
223			};
224
225			/omit-if-no-ref/ i2s0a_sdi_p1_4: i2s0a_sdi_p1_4 {
226				pinmux = <MAX32_PINMUX(1, 4, AF1)>;
227			};
228
229			/omit-if-no-ref/ tmr3b_ioa_p1_4: tmr3b_ioa_p1_4 {
230				pinmux = <MAX32_PINMUX(1, 4, AF2)>;
231			};
232
233			/omit-if-no-ref/ i2s0a_sdo_p1_5: i2s0a_sdo_p1_5 {
234				pinmux = <MAX32_PINMUX(1, 5, AF1)>;
235			};
236
237			/omit-if-no-ref/ tmr3b_iob_p1_5: tmr3b_iob_p1_5 {
238				pinmux = <MAX32_PINMUX(1, 5, AF2)>;
239			};
240
241			/omit-if-no-ref/ tmr3a_ioa_p1_6: tmr3a_ioa_p1_6 {
242				pinmux = <MAX32_PINMUX(1, 6, AF1)>;
243			};
244
245			/omit-if-no-ref/ ble_ant_ctrl2_p1_6: ble_ant_ctrl2_p1_6 {
246				pinmux = <MAX32_PINMUX(1, 6, AF2)>;
247			};
248
249			/omit-if-no-ref/ tmr3a_iob_p1_7: tmr3a_iob_p1_7 {
250				pinmux = <MAX32_PINMUX(1, 7, AF1)>;
251			};
252
253			/omit-if-no-ref/ ble_ant_ctrl3_p1_7: ble_ant_ctrl3_p1_7 {
254				pinmux = <MAX32_PINMUX(1, 7, AF2)>;
255			};
256
257			/omit-if-no-ref/ ain12_p2_4: ain12_p2_4 {
258				pinmux = <MAX32_PINMUX(2, 4, AF1)>;
259			};
260
261			/omit-if-no-ref/ lptmr0b_ioa_p2_4: lptmr0b_ioa_p2_4 {
262				pinmux = <MAX32_PINMUX(2, 4, AF2)>;
263			};
264
265			/omit-if-no-ref/ ain13_p2_5: ain13_p2_5 {
266				pinmux = <MAX32_PINMUX(2, 5, AF1)>;
267			};
268
269			/omit-if-no-ref/ lptmr1b_ioa_p2_5: lptmr1b_ioa_p2_5 {
270				pinmux = <MAX32_PINMUX(2, 5, AF2)>;
271			};
272
273			/omit-if-no-ref/ lptmr0_clk_p2_6: lptmr0_clk_p2_6 {
274				pinmux = <MAX32_PINMUX(2, 6, AF1)>;
275			};
276
277			/omit-if-no-ref/ lpuartb_r_p2_6: lpuartb_r_p2_6 {
278				pinmux = <MAX32_PINMUX(2, 6, AF2)>;
279			};
280
281			/omit-if-no-ref/ x_p2_6: x_p2_6 {
282				pinmux = <MAX32_PINMUX(2, 6, AF3)>;
283			};
284
285			/omit-if-no-ref/ lptmr1_clk_p2_7: lptmr1_clk_p2_7 {
286				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
287			};
288
289			/omit-if-no-ref/ lpuartb_tx_p2_7: lpuartb_tx_p2_7 {
290				pinmux = <MAX32_PINMUX(2, 7, AF2)>;
291			};
292		};
293	};
294};
295