1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9#include <zephyr/dt-bindings/dma/max32675_dma.h>
10
11&flash0 {
12	reg = <0x10000000 DT_SIZE_K(384)>;
13};
14
15&sram0 {
16	reg = <0x20000000 DT_SIZE_K(16)>;
17};
18
19&clk_inro {
20	clock-frequency = <DT_FREQ_K(80)>;
21};
22
23/delete-node/ &clk_iso;
24/delete-node/ &uart1;
25
26/* MAX32675 extra peripherals. */
27/ {
28	soc {
29		sram1: memory@20004000 {
30			compatible = "mmio-sram";
31			reg = <0x20004000 DT_SIZE_K(16)>;
32		};
33
34		sram2: memory@20008000 {
35			compatible = "mmio-sram";
36			reg = <0x20008000 DT_SIZE_K(32)>;
37		};
38
39		sram3: memory@20010000 {
40			compatible = "mmio-sram";
41			reg = <0x20010000 DT_SIZE_K(64)>;
42		};
43
44		sram4: memory@20020000 {
45			compatible = "mmio-sram";
46			reg = <0x20020000 DT_SIZE_K(4)>;
47		};
48
49		sram5: memory@20021000 {
50			compatible = "mmio-sram";
51			reg = <0x20021000 DT_SIZE_K(4)>;
52		};
53
54		sram6: memory@20022000 {
55			compatible = "mmio-sram";
56			reg = <0x20022000 DT_SIZE_K(8)>;
57		};
58
59		sram7: memory@20024000 {
60			compatible = "mmio-sram";
61			reg = <0x20024000 DT_SIZE_K(16)>;
62		};
63
64		dma0: dma@40028000 {
65			compatible = "adi,max32-dma";
66			reg = <0x40028000 0x1000>;
67			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
68			interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>;
69			dma-channels = <8>;
70			status = "disabled";
71			#dma-cells = <2>;
72		};
73
74		spi1: spi@40047000 {
75			compatible = "adi,max32-spi";
76			reg = <0x40047000 0x1000>;
77			#address-cells = <1>;
78			#size-cells = <0>;
79			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
80			interrupts = <17 0>;
81			status = "disabled";
82		};
83
84		lptimer0: timer@40114000 {
85			compatible = "adi,max32-timer";
86			reg = <0x40114000 0x1000>;
87			interrupts = <9 0>;
88			status = "disabled";
89			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
90			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
91			prescaler = <1>;
92		};
93	};
94};
95