1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
8
9/ {
10	soc {
11		pinctrl: pin-controller@40008000 {
12
13			/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
14				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
15			};
16
17			/omit-if-no-ref/ tmr0c_ia_p0_0: tmr0c_ia_p0_0 {
18				pinmux = <MAX32_PINMUX(0, 0, AF3)>;
19			};
20
21			/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
22				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
23			};
24
25			/omit-if-no-ref/ tmr0c_o_p0_1: tmr0c_o_p0_1 {
26				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
27			};
28
29			/omit-if-no-ref/ spi0_miso_p0_2: spi0_miso_p0_2 {
30				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
31			};
32
33			/omit-if-no-ref/ uart1b_rx_p0_2: uart1b_rx_p0_2 {
34				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
35			};
36
37			/omit-if-no-ref/ tmr1c_ia_p0_2: tmr1c_ia_p0_2 {
38				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
39			};
40
41			/omit-if-no-ref/ spi0_mosi_p0_3: spi0_mosi_p0_3 {
42				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
43			};
44
45			/omit-if-no-ref/ uart1b_tx_p0_3: uart1b_tx_p0_3 {
46				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
47			};
48
49			/omit-if-no-ref/ tmr1c_oa_p0_3: tmr1c_oa_p0_3 {
50				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
51			};
52
53			/omit-if-no-ref/ spi0_sck_p0_4: spi0_sck_p0_4 {
54				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
55			};
56
57			/omit-if-no-ref/ uart1b_cts_p0_4: uart1b_cts_p0_4 {
58				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
59			};
60
61			/omit-if-no-ref/ tmr2c_ia_p0_4: tmr2c_ia_p0_4 {
62				pinmux = <MAX32_PINMUX(0, 4, AF3)>;
63			};
64
65			/omit-if-no-ref/ spi0_ss0_p0_5: spi0_ss0_p0_5 {
66				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
67			};
68
69			/omit-if-no-ref/ uart1b_rts_p0_5: uart1b_rts_p0_5 {
70				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
71			};
72
73			/omit-if-no-ref/ tmr2c_oa_p0_5: tmr2c_oa_p0_5 {
74				pinmux = <MAX32_PINMUX(0, 5, AF3)>;
75			};
76
77			/omit-if-no-ref/ div_clk_outa_p0_5: div_clk_outa_p0_5 {
78				pinmux = <MAX32_PINMUX(0, 5, AF4)>;
79			};
80
81			/omit-if-no-ref/ i2c0_scl_p0_6: i2c0_scl_p0_6 {
82				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
83			};
84
85			/omit-if-no-ref/ lptmr0b_ia_p0_6: lptmr0b_ia_p0_6 {
86				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
87			};
88
89			/omit-if-no-ref/ tmr3c_ia_p0_6: tmr3c_ia_p0_6 {
90				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
91			};
92
93			/omit-if-no-ref/ i2c0_sda_p0_7: i2c0_sda_p0_7 {
94				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
95			};
96
97			/omit-if-no-ref/ lptmr0b_oa_p0_7: lptmr0b_oa_p0_7 {
98				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
99			};
100
101			/omit-if-no-ref/ tmr3c_oa_p0_7: tmr3c_oa_p0_7 {
102				pinmux = <MAX32_PINMUX(0, 7, AF3)>;
103			};
104
105			/omit-if-no-ref/ uart0a_rx_p0_8: uart0a_rx_p0_8 {
106				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
107			};
108
109			/omit-if-no-ref/ i2s0_sdo_p0_8: i2s0_sdo_p0_8 {
110				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
111			};
112
113			/omit-if-no-ref/ tmr0c_ia_p0_8: tmr0c_ia_p0_8 {
114				pinmux = <MAX32_PINMUX(0, 8, AF3)>;
115			};
116
117			/omit-if-no-ref/ uart0a_tx_p0_9: uart0a_tx_p0_9 {
118				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
119			};
120
121			/omit-if-no-ref/ i2s0_lrclk_p0_9: i2s0_lrclk_p0_9 {
122				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
123			};
124
125			/omit-if-no-ref/ tmr0c_oa_p0_9: tmr0c_oa_p0_9 {
126				pinmux = <MAX32_PINMUX(0, 9, AF3)>;
127			};
128
129			/omit-if-no-ref/ uart0a_cts_p0_10: uart0a_cts_p0_10 {
130				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
131			};
132
133			/omit-if-no-ref/ i2s0_bclk_p0_10: i2s0_bclk_p0_10 {
134				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
135			};
136
137			/omit-if-no-ref/ tmr1c_ia_p0_10: tmr1c_ia_p0_10 {
138				pinmux = <MAX32_PINMUX(0, 10, AF3)>;
139			};
140
141			/omit-if-no-ref/ div_clk_outb_p0_10: div_clk_outb_p0_10 {
142				pinmux = <MAX32_PINMUX(0, 10, AF4)>;
143			};
144
145			/omit-if-no-ref/ uart0a_rts_p0_11: uart0a_rts_p0_11 {
146				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
147			};
148
149			/omit-if-no-ref/ i2s0_sdi_p0_11: i2s0_sdi_p0_11 {
150				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
151			};
152
153			/omit-if-no-ref/ tmr1c_oa_p0_11: tmr1c_oa_p0_11 {
154				pinmux = <MAX32_PINMUX(0, 11, AF3)>;
155			};
156
157			/omit-if-no-ref/ i2c1_scl_p0_12: i2c1_scl_p0_12 {
158				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
159			};
160
161			/omit-if-no-ref/ ext_clk2_p0_12: ext_clk2_p0_12 {
162				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
163			};
164
165			/omit-if-no-ref/ tmr2c_ia_p0_12: tmr2c_ia_p0_12 {
166				pinmux = <MAX32_PINMUX(0, 12, AF3)>;
167			};
168
169			/omit-if-no-ref/ ext_clk1_p0_12: ext_clk1_p0_12 {
170				pinmux = <MAX32_PINMUX(0, 12, AF4)>;
171			};
172
173			/omit-if-no-ref/ i2c1_sda_p0_13: i2c1_sda_p0_13 {
174				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
175			};
176
177			/omit-if-no-ref/ cal32k_p0_13: cal32k_p0_13 {
178				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
179			};
180
181			/omit-if-no-ref/ tmr2c_oa_p0_13: tmr2c_oa_p0_13 {
182				pinmux = <MAX32_PINMUX(0, 13, AF3)>;
183			};
184
185			/omit-if-no-ref/ spi1_ss0_p0_13: spi1_ss0_p0_13 {
186				pinmux = <MAX32_PINMUX(0, 13, AF4)>;
187			};
188
189			/omit-if-no-ref/ spi1_miso_p0_14: spi1_miso_p0_14 {
190				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
191			};
192
193			/omit-if-no-ref/ uart2b_rx_p0_14: uart2b_rx_p0_14 {
194				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
195			};
196
197			/omit-if-no-ref/ tmr3c_ia_p0_14: tmr3c_ia_p0_14 {
198				pinmux = <MAX32_PINMUX(0, 14, AF3)>;
199			};
200
201			/omit-if-no-ref/ spi1_mosi_p0_15: spi1_mosi_p0_15 {
202				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
203			};
204
205			/omit-if-no-ref/ uart2b_tx_p0_15: uart2b_tx_p0_15 {
206				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
207			};
208
209			/omit-if-no-ref/ tmr3c_oa_p0_15: tmr3c_oa_p0_15 {
210				pinmux = <MAX32_PINMUX(0, 15, AF3)>;
211			};
212
213			/omit-if-no-ref/ spi1_sck_p0_16: spi1_sck_p0_16 {
214				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
215			};
216
217			/omit-if-no-ref/ uart2b_cts_p0_16: uart2b_cts_p0_16 {
218				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
219			};
220
221			/omit-if-no-ref/ tmr0c_ia_p0_16: tmr0c_ia_p0_16 {
222				pinmux = <MAX32_PINMUX(0, 16, AF3)>;
223			};
224
225			/omit-if-no-ref/ spi1_ss0_p0_17: spi1_ss0_p0_17 {
226				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
227			};
228
229			/omit-if-no-ref/ uart2b_rts_p0_17: uart2b_rts_p0_17 {
230				pinmux = <MAX32_PINMUX(0, 17, AF2)>;
231			};
232
233			/omit-if-no-ref/ tmr0c_oa_p0_17: tmr0c_oa_p0_17 {
234				pinmux = <MAX32_PINMUX(0, 17, AF3)>;
235			};
236
237			/omit-if-no-ref/ i2c2_scl_p0_18: i2c2_scl_p0_18 {
238				pinmux = <MAX32_PINMUX(0, 18, AF1)>;
239			};
240
241			/omit-if-no-ref/ tmr1c_ia_p0_18: tmr1c_ia_p0_18 {
242				pinmux = <MAX32_PINMUX(0, 18, AF3)>;
243			};
244
245			/omit-if-no-ref/ i2c2_sda_p0_19: i2c2_sda_p0_19 {
246				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
247			};
248
249			/omit-if-no-ref/ tmr1c_oa_p0_19: tmr1c_oa_p0_19 {
250				pinmux = <MAX32_PINMUX(0, 19, AF3)>;
251			};
252
253			/omit-if-no-ref/ cm4_rx_p0_20: cm4_rx_p0_20 {
254				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
255			};
256
257			/omit-if-no-ref/ tmr2c_ia_p0_20: tmr2c_ia_p0_20 {
258				pinmux = <MAX32_PINMUX(0, 20, AF3)>;
259			};
260
261			/omit-if-no-ref/ swdclkb_p0_20: swdclkb_p0_20 {
262				pinmux = <MAX32_PINMUX(0, 20, AF4)>;
263			};
264
265			/omit-if-no-ref/ cm4_tx_p0_21: cm4_tx_p0_21 {
266				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
267			};
268
269			/omit-if-no-ref/ tmr2c_oa_p0_21: tmr2c_oa_p0_21 {
270				pinmux = <MAX32_PINMUX(0, 21, AF3)>;
271			};
272
273			/omit-if-no-ref/ lptmr1a_ia_p0_22: lptmr1a_ia_p0_22 {
274				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
275			};
276
277			/omit-if-no-ref/ tmr3c_ia_p0_22: tmr3c_ia_p0_22 {
278				pinmux = <MAX32_PINMUX(0, 22, AF3)>;
279			};
280
281			/omit-if-no-ref/ swdiob_p0_22: swdiob_p0_22 {
282				pinmux = <MAX32_PINMUX(0, 22, AF4)>;
283			};
284
285			/omit-if-no-ref/ lptmr1a_oa_p0_23: lptmr1a_oa_p0_23 {
286				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
287			};
288
289			/omit-if-no-ref/ tmr3c_oa_p0_23: tmr3c_oa_p0_23 {
290				pinmux = <MAX32_PINMUX(0, 23, AF3)>;
291			};
292
293			/omit-if-no-ref/ lpuart0_cts_p0_24: lpuart0_cts_p0_24 {
294				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
295			};
296
297			/omit-if-no-ref/ uart0b_rx_p0_24: uart0b_rx_p0_24 {
298				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
299			};
300
301			/omit-if-no-ref/ tmr0c_ia_p0_24: tmr0c_ia_p0_24 {
302				pinmux = <MAX32_PINMUX(0, 24, AF3)>;
303			};
304
305			/omit-if-no-ref/ lpuart0_rts_p0_25: lpuart0_rts_p0_25 {
306				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
307			};
308
309			/omit-if-no-ref/ uart0b_tx_p0_25: uart0b_tx_p0_25 {
310				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
311			};
312
313			/omit-if-no-ref/ tmr0c_oa_p0_25: tmr0c_oa_p0_25 {
314				pinmux = <MAX32_PINMUX(0, 25, AF3)>;
315			};
316
317			/omit-if-no-ref/ lpuart0_rx_p0_26: lpuart0_rx_p0_26 {
318				pinmux = <MAX32_PINMUX(0, 26, AF1)>;
319			};
320
321			/omit-if-no-ref/ uart0b_cts_p0_26: uart0b_cts_p0_26 {
322				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
323			};
324
325			/omit-if-no-ref/ tmr1c_ia_p0_26: tmr1c_ia_p0_26 {
326				pinmux = <MAX32_PINMUX(0, 26, AF3)>;
327			};
328
329			/omit-if-no-ref/ lpuart0_tx_p0_27: lpuart0_tx_p0_27 {
330				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
331			};
332
333			/omit-if-no-ref/ uart0b_rts_p0_27: uart0b_rts_p0_27 {
334				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
335			};
336
337			/omit-if-no-ref/ tmr1c_oa_p0_27: tmr1c_oa_p0_27 {
338				pinmux = <MAX32_PINMUX(0, 27, AF3)>;
339			};
340
341			/omit-if-no-ref/ uart1a_rx_p0_28: uart1a_rx_p0_28 {
342				pinmux = <MAX32_PINMUX(0, 28, AF1)>;
343			};
344
345			/omit-if-no-ref/ tmr2c_ia_p0_28: tmr2c_ia_p0_28 {
346				pinmux = <MAX32_PINMUX(0, 28, AF3)>;
347			};
348
349			/omit-if-no-ref/ uart1a_tx_p0_29: uart1a_tx_p0_29 {
350				pinmux = <MAX32_PINMUX(0, 29, AF1)>;
351			};
352
353			/omit-if-no-ref/ tmr2c_oa_p0_29: tmr2c_oa_p0_29 {
354				pinmux = <MAX32_PINMUX(0, 29, AF3)>;
355			};
356
357			/omit-if-no-ref/ uart1a_cts_p0_30: uart1a_cts_p0_30 {
358				pinmux = <MAX32_PINMUX(0, 30, AF1)>;
359			};
360
361			/omit-if-no-ref/ tmr3c_ia_p0_30: tmr3c_ia_p0_30 {
362				pinmux = <MAX32_PINMUX(0, 30, AF3)>;
363			};
364
365		};
366	};
367};
368