1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
8
9/ {
10	soc {
11		pinctrl: pin-controller@40008000 {
12
13			/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
14				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
15			};
16
17			/omit-if-no-ref/ pt0b_p0_0: pt0b_p0_0 {
18				pinmux = <MAX32_PINMUX(0, 0, AF2)>;
19			};
20
21			/omit-if-no-ref/ tmr0c_oa_p0_0: tmr0c_oa_p0_0 {
22				pinmux = <MAX32_PINMUX(0, 0, AF3)>;
23			};
24
25			/omit-if-no-ref/ tmr1d_oa_p0_0: tmr1d_oa_p0_0 {
26				pinmux = <MAX32_PINMUX(0, 0, AF4)>;
27			};
28
29			/omit-if-no-ref/ adc_trig_e_p0_0: adc_trig_e_p0_0 {
30				pinmux = <MAX32_PINMUX(0, 0, AF5)>;
31			};
32
33			/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
34				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
35			};
36
37			/omit-if-no-ref/ pt1b_p0_1: pt1b_p0_1 {
38				pinmux = <MAX32_PINMUX(0, 1, AF2)>;
39			};
40
41			/omit-if-no-ref/ tmr0c_ia_p0_1: tmr0c_ia_p0_1 {
42				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
43			};
44
45			/omit-if-no-ref/ tmr1d_ia_p0_1: tmr1d_ia_p0_1 {
46				pinmux = <MAX32_PINMUX(0, 1, AF4)>;
47			};
48
49			/omit-if-no-ref/ spi0a_cito_p0_2: spi0a_cito_p0_2 {
50				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
51			};
52
53			/omit-if-no-ref/ uart1b_tx_p0_2: uart1b_tx_p0_2 {
54				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
55			};
56
57			/omit-if-no-ref/ tmr0c_ia_p0_2: tmr0c_ia_p0_2 {
58				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
59			};
60
61			/omit-if-no-ref/ pt0d_p0_2: pt0d_p0_2 {
62				pinmux = <MAX32_PINMUX(0, 2, AF4)>;
63			};
64
65			/omit-if-no-ref/ i2s0e_sdo_p0_2: i2s0e_sdo_p0_2 {
66				pinmux = <MAX32_PINMUX(0, 2, AF5)>;
67			};
68
69			/omit-if-no-ref/ spi0a_copi_p0_3: spi0a_copi_p0_3 {
70				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
71			};
72
73			/omit-if-no-ref/ uart1b_rx_p0_3: uart1b_rx_p0_3 {
74				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
75			};
76
77			/omit-if-no-ref/ tmr0c_oa_p0_3: tmr0c_oa_p0_3 {
78				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
79			};
80
81			/omit-if-no-ref/ pt1d_p0_3: pt1d_p0_3 {
82				pinmux = <MAX32_PINMUX(0, 3, AF4)>;
83			};
84
85			/omit-if-no-ref/ i2s0e_sdi_p0_3: i2s0e_sdi_p0_3 {
86				pinmux = <MAX32_PINMUX(0, 3, AF5)>;
87			};
88
89			/omit-if-no-ref/ spi0a_sck_p0_4: spi0a_sck_p0_4 {
90				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
91			};
92
93			/omit-if-no-ref/ uart1b_cts_p0_4: uart1b_cts_p0_4 {
94				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
95			};
96
97			/omit-if-no-ref/ tmr1c_ia_p0_4: tmr1c_ia_p0_4 {
98				pinmux = <MAX32_PINMUX(0, 4, AF3)>;
99			};
100
101			/omit-if-no-ref/ pt2d_p0_4: pt2d_p0_4 {
102				pinmux = <MAX32_PINMUX(0, 4, AF4)>;
103			};
104
105			/omit-if-no-ref/ i2s0e_bclk_p0_4: i2s0e_bclk_p0_4 {
106				pinmux = <MAX32_PINMUX(0, 4, AF5)>;
107			};
108
109			/omit-if-no-ref/ spi0a_ts0_p0_5: spi0a_ts0_p0_5 {
110				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
111			};
112
113			/omit-if-no-ref/ uart1b_rts_p0_5: uart1b_rts_p0_5 {
114				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
115			};
116
117			/omit-if-no-ref/ tmr1c_oa_p0_5: tmr1c_oa_p0_5 {
118				pinmux = <MAX32_PINMUX(0, 5, AF3)>;
119			};
120
121			/omit-if-no-ref/ pt3d_p0_5: pt3d_p0_5 {
122				pinmux = <MAX32_PINMUX(0, 5, AF4)>;
123			};
124
125			/omit-if-no-ref/ i2s0e_lrclk_p0_5: i2s0e_lrclk_p0_5 {
126				pinmux = <MAX32_PINMUX(0, 5, AF5)>;
127			};
128
129			/omit-if-no-ref/ i2c1a_scl_p0_6: i2c1a_scl_p0_6 {
130				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
131			};
132
133			/omit-if-no-ref/ can0b_rx_p0_6: can0b_rx_p0_6 {
134				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
135			};
136
137			/omit-if-no-ref/ tmr2c_ia_p0_6: tmr2c_ia_p0_6 {
138				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
139			};
140
141			/omit-if-no-ref/ hf_ext_clk_p0_6: hf_ext_clk_p0_6 {
142				pinmux = <MAX32_PINMUX(0, 6, AF4)>;
143			};
144
145			/omit-if-no-ref/ pt2e_p0_6: pt2e_p0_6 {
146				pinmux = <MAX32_PINMUX(0, 6, AF5)>;
147			};
148
149			/omit-if-no-ref/ spi1a_miso_p0_7: spi1a_miso_p0_7 {
150				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
151			};
152
153			/omit-if-no-ref/ uart0b_cts_p0_7: uart0b_cts_p0_7 {
154				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
155			};
156
157			/omit-if-no-ref/ tmr2c_ia_p0_7: tmr2c_ia_p0_7 {
158				pinmux = <MAX32_PINMUX(0, 7, AF3)>;
159			};
160
161			/omit-if-no-ref/ uart0d_rx_p0_7: uart0d_rx_p0_7 {
162				pinmux = <MAX32_PINMUX(0, 7, AF4)>;
163			};
164
165			/omit-if-no-ref/ spi1a_mosi_p0_8: spi1a_mosi_p0_8 {
166				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
167			};
168
169			/omit-if-no-ref/ uart0b_rts_p0_8: uart0b_rts_p0_8 {
170				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
171			};
172
173			/omit-if-no-ref/ tmr2c_oa_p0_8: tmr2c_oa_p0_8 {
174				pinmux = <MAX32_PINMUX(0, 8, AF3)>;
175			};
176
177			/omit-if-no-ref/ uart0d_tx_p0_8: uart0d_tx_p0_8 {
178				pinmux = <MAX32_PINMUX(0, 8, AF4)>;
179			};
180
181			/omit-if-no-ref/ i2c1a_sda_p0_9: i2c1a_sda_p0_9 {
182				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
183			};
184
185			/omit-if-no-ref/ can0b_tx_p0_9: can0b_tx_p0_9 {
186				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
187			};
188
189			/omit-if-no-ref/ tmr2c_oa_p0_9: tmr2c_oa_p0_9 {
190				pinmux = <MAX32_PINMUX(0, 9, AF3)>;
191			};
192
193			/omit-if-no-ref/ adc_trig_d_p0_9: adc_trig_d_p0_9 {
194				pinmux = <MAX32_PINMUX(0, 9, AF4)>;
195			};
196
197			/omit-if-no-ref/ pt3e_p0_9: pt3e_p0_9 {
198				pinmux = <MAX32_PINMUX(0, 9, AF5)>;
199			};
200
201			/omit-if-no-ref/ uart0a_tx_p0_10: uart0a_tx_p0_10 {
202				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
203			};
204
205			/omit-if-no-ref/ spi1b_ts0_p0_10: spi1b_ts0_p0_10 {
206				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
207			};
208
209			/omit-if-no-ref/ ain3_p0_10: ain3_p0_10 {
210				pinmux = <MAX32_PINMUX(0, 10, AF4)>;
211			};
212
213			/omit-if-no-ref/ uart0a_rx_p0_11: uart0a_rx_p0_11 {
214				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
215			};
216
217			/omit-if-no-ref/ spi1b_sck_p0_11: spi1b_sck_p0_11 {
218				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
219			};
220
221			/omit-if-no-ref/ cal32k_p0_11: cal32k_p0_11 {
222				pinmux = <MAX32_PINMUX(0, 11, AF3)>;
223			};
224
225			/omit-if-no-ref/ ain2_p0_11: ain2_p0_11 {
226				pinmux = <MAX32_PINMUX(0, 11, AF4)>;
227			};
228
229			/omit-if-no-ref/ lp_ext_clk_p0_11: lp_ext_clk_p0_11 {
230				pinmux = <MAX32_PINMUX(0, 11, AF5)>;
231			};
232
233			/omit-if-no-ref/ i2c0a_scl_p0_12: i2c0a_scl_p0_12 {
234				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
235			};
236
237			/omit-if-no-ref/ spi1b_coti_p0_12: spi1b_coti_p0_12 {
238				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
239			};
240
241			/omit-if-no-ref/ lptmr0c_ia_p0_12: lptmr0c_ia_p0_12 {
242				pinmux = <MAX32_PINMUX(0, 12, AF3)>;
243			};
244
245			/omit-if-no-ref/ ain1_p0_12: ain1_p0_12 {
246				pinmux = <MAX32_PINMUX(0, 12, AF4)>;
247			};
248
249			/omit-if-no-ref/ lptmr0e_oan_p0_12: lptmr0e_oan_p0_12 {
250				pinmux = <MAX32_PINMUX(0, 12, AF5)>;
251			};
252
253			/omit-if-no-ref/ i2c0a_sda_p0_13: i2c0a_sda_p0_13 {
254				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
255			};
256
257			/omit-if-no-ref/ spi1b_cito_p0_13: spi1b_cito_p0_13 {
258				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
259			};
260
261			/omit-if-no-ref/ lptmr0c_oa_p0_13: lptmr0c_oa_p0_13 {
262				pinmux = <MAX32_PINMUX(0, 13, AF3)>;
263			};
264
265			/omit-if-no-ref/ ain0_p0_13: ain0_p0_13 {
266				pinmux = <MAX32_PINMUX(0, 13, AF4)>;
267			};
268
269
270
271			/omit-if-no-ref/ pt0a_p0_14: pt0a_p0_14 {
272				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
273			};
274
275			/omit-if-no-ref/ pt1a_p0_15: pt1a_p0_15 {
276				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
277			};
278
279			/omit-if-no-ref/ can0b_rx_p0_15: can0b_rx_p0_15 {
280				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
281			};
282
283			/omit-if-no-ref/ tmr2c_ia_p0_15: tmr2c_ia_p0_15 {
284				pinmux = <MAX32_PINMUX(0, 15, AF3)>;
285			};
286
287			/omit-if-no-ref/ tmr0d_ia_p0_15: tmr0d_ia_p0_15 {
288				pinmux = <MAX32_PINMUX(0, 15, AF4)>;
289			};
290
291			/omit-if-no-ref/ pt2a_p0_16: pt2a_p0_16 {
292				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
293			};
294
295			/omit-if-no-ref/ can0b_tx_p0_16: can0b_tx_p0_16 {
296				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
297			};
298
299			/omit-if-no-ref/ tmr2c_oa_p0_16: tmr2c_oa_p0_16 {
300				pinmux = <MAX32_PINMUX(0, 16, AF3)>;
301			};
302
303			/omit-if-no-ref/ tmr0d_oa_p0_16: tmr0d_oa_p0_16 {
304				pinmux = <MAX32_PINMUX(0, 16, AF4)>;
305			};
306
307			/omit-if-no-ref/ spi1a_sck_p0_17: spi1a_sck_p0_17 {
308				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
309			};
310
311			/omit-if-no-ref/ adc_trig_c_p0_17: adc_trig_c_p0_17 {
312				pinmux = <MAX32_PINMUX(0, 17, AF3)>;
313			};
314
315			/omit-if-no-ref/ uart0d_cts_p0_17: uart0d_cts_p0_17 {
316				pinmux = <MAX32_PINMUX(0, 17, AF4)>;
317			};
318
319			/omit-if-no-ref/ spi1a_ss0_p0_18: spi1a_ss0_p0_18 {
320				pinmux = <MAX32_PINMUX(0, 18, AF1)>;
321			};
322
323			/omit-if-no-ref/ uart0d_rts_p0_17: uart0d_rts_p0_17 {
324				pinmux = <MAX32_PINMUX(0, 18, AF4)>;
325			};
326
327			/omit-if-no-ref/ uart0a_rts_p0_19: uart0a_rts_p0_19 {
328				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
329			};
330
331			/omit-if-no-ref/ tmrt1c_ia_p0_19: tmrt1c_ia_p0_19 {
332				pinmux = <MAX32_PINMUX(0, 19, AF3)>;
333			};
334
335			/omit-if-no-ref/ uart0a_cts_p0_20: uart0a_cts_p0_20 {
336				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
337			};
338
339			/omit-if-no-ref/ tmrt1c_oa_p0_20: tmrt1c_oa_p0_20 {
340				pinmux = <MAX32_PINMUX(0, 20, AF3)>;
341			};
342		};
343	};
344};
345