1 /*
2 * Copyright (c) 2023 ITE Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "udc_common.h"
8
9 #include <soc.h>
10 #include <soc_dt.h>
11 #include <zephyr/pm/policy.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/drivers/interrupt_controller/wuc_ite_it8xxx2.h>
15 #include <zephyr/dt-bindings/interrupt-controller/it8xxx2-wuc.h>
16 LOG_MODULE_REGISTER(udc_it82xx2, CONFIG_UDC_DRIVER_LOG_LEVEL);
17
18 #define DT_DRV_COMPAT ite_it82xx2_usb
19
20 /* TODO: Replace this definition by Kconfig option */
21 #define USB_DEVICE_CONFIG_SOF_NOTIFICATIONS (0U)
22
23 #define IT8XXX2_IS_EXTEND_ENDPOINT(n) (USB_EP_GET_IDX(n) >= 4)
24
25 #define IT82xx2_STATE_OUT_SHARED_FIFO_BUSY 0
26
27 /* Shared FIFO number including FIFO_1/2/3 */
28 #define SHARED_FIFO_NUM 3
29
30 /* The related definitions of the register dc_line_status: 0x51 */
31 #define RX_LINE_STATE_MASK (RX_LINE_FULL_SPD | RX_LINE_LOW_SPD)
32 #define RX_LINE_LOW_SPD 0x02
33 #define RX_LINE_FULL_SPD 0x01
34 #define RX_LINE_RESET 0x00
35
36 #define DC_ADDR_NULL 0x00
37 #define DC_ADDR_MASK 0x7F
38
39 /* EPN Extend Control 2 Register Mask Definition */
40 #define COMPLETED_TRANS 0xF0
41
42 /* The related definitions of the register EP STATUS:
43 * 0x41/0x45/0x49/0x4D
44 */
45 #define EP_STATUS_ERROR 0x0F
46
47 /* ENDPOINT[3..0]_CONTROL_REG */
48 #define ENDPOINT_EN BIT(0)
49 #define ENDPOINT_RDY BIT(1)
50
51 /* The bit definitions of the register EP RX/TX FIFO Control:
52 * EP_RX_FIFO_CONTROL: 0X64/0x84/0xA4/0xC4
53 * EP_TX_FIFO_CONTROL: 0X74/0x94/0xB4/0xD4
54 */
55 #define FIFO_FORCE_EMPTY BIT(0)
56
57 /* The bit definitions of the register Host/Device Control: 0XE0 */
58 #define RESET_CORE BIT(1)
59
60 /* ENDPOINT[3..0]_STATUS_REG */
61 #define DC_STALL_SENT BIT(5)
62
63 /* DC_INTERRUPT_STATUS_REG */
64 #define DC_TRANS_DONE BIT(0)
65 #define DC_RESUME_EVENT BIT(1)
66 #define DC_RESET_EVENT BIT(2)
67 #define DC_SOF_RECEIVED BIT(3)
68 #define DC_NAK_SENT_INT BIT(4)
69
70 /* DC_CONTROL_REG */
71 #define DC_GLOBAL_ENABLE BIT(0)
72 #define DC_TX_LINE_STATE_DM BIT(1)
73 #define DC_DIRECT_CONTROL BIT(3)
74 #define DC_FULL_SPEED_LINE_POLARITY BIT(4)
75 #define DC_FULL_SPEED_LINE_RATE BIT(5)
76 #define DC_CONNECT_TO_HOST BIT(6) /* internal pull-up */
77
78 /* ENDPOINT[3..0]_CONTROL_REG */
79 #define ENDPOINT_ENABLE_BIT BIT(0)
80 #define ENDPOINT_READY_BIT BIT(1)
81 #define ENDPOINT_OUTDATA_SEQ_BIT BIT(2)
82 #define ENDPOINT_SEND_STALL_BIT BIT(3)
83 #define ENDPOINT_ISO_ENABLE_BIT BIT(4)
84 #define ENDPOINT_DIRECTION_BIT BIT(5)
85
86 /* Bit [1:0] represents the TRANSACTION_TYPE as follows: */
87 enum it82xx2_transaction_types {
88 DC_SETUP_TRANS = 0,
89 DC_IN_TRANS,
90 DC_OUTDATA_TRANS,
91 DC_ALL_TRANS
92 };
93
94 enum it82xx2_event_type {
95 IT82xx2_EVT_XFER,
96 IT82xx2_EVT_SETUP_TOKEN,
97 IT82xx2_EVT_OUT_TOKEN,
98 IT82xx2_EVT_IN_TOKEN,
99 };
100
101 struct it82xx2_ep_event {
102 sys_snode_t node;
103 const struct device *dev;
104 uint8_t ep;
105 enum it82xx2_event_type event;
106 };
107
108 K_MSGQ_DEFINE(evt_msgq, sizeof(struct it82xx2_ep_event),
109 CONFIG_UDC_IT82xx2_EVENT_COUNT, sizeof(uint32_t));
110
111 struct usb_it8xxx2_wuc {
112 /* WUC control device structure */
113 const struct device *dev;
114 /* WUC pin mask */
115 uint8_t mask;
116 };
117
118 struct it82xx2_data {
119 const struct device *dev;
120
121 struct k_fifo fifo;
122 struct k_work_delayable suspended_work;
123
124 struct k_thread thread_data;
125 struct k_sem suspended_sem;
126
127 /* shared OUT FIFO state */
128 atomic_t out_fifo_state;
129
130 /* FIFO_1/2/3 semaphore */
131 struct k_sem fifo_sem[SHARED_FIFO_NUM];
132
133 /* Record if the previous transaction of endpoint0 is STALL */
134 bool stall_is_sent;
135 };
136
137 struct usb_it82xx2_config {
138 struct usb_it82xx2_regs *const base;
139 const struct pinctrl_dev_config *pcfg;
140 const struct usb_it8xxx2_wuc wuc;
141 uint8_t usb_irq;
142 uint8_t wu_irq;
143 struct udc_ep_config *ep_cfg_in;
144 struct udc_ep_config *ep_cfg_out;
145 void (*make_thread)(const struct device *dev);
146 };
147
148 enum it82xx2_ep_ctrl {
149 EP_IN_DIRECTION_SET,
150 EP_STALL_SEND,
151 EP_IOS_ENABLE,
152 EP_ENABLE,
153 EP_DATA_SEQ_1,
154 EP_DATA_SEQ_TOGGLE,
155 EP_READY_ENABLE,
156 };
157
158 /* The ep_fifo_res[ep_idx % SHARED_FIFO_NUM] where the SHARED_FIFO_NUM is 3 represents the
159 * EP mapping because when (ep_idx % SHARED_FIFO_NUM) is 3, it actually means the EP0.
160 */
161 static const uint8_t ep_fifo_res[SHARED_FIFO_NUM] = {3, 1, 2};
162
it82xx2_get_ext_ctrl(const struct device * dev,const uint8_t ep_idx,const enum it82xx2_ep_ctrl ctrl)163 static volatile void *it82xx2_get_ext_ctrl(const struct device *dev, const uint8_t ep_idx,
164 const enum it82xx2_ep_ctrl ctrl)
165 {
166 uint8_t idx;
167 const struct usb_it82xx2_config *config = dev->config;
168 struct usb_it82xx2_regs *const usb_regs = config->base;
169 union epn0n1_extend_ctrl_reg *epn0n1_ext_ctrl =
170 usb_regs->fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl;
171 struct epn_ext_ctrl_regs *ext_ctrl =
172 usb_regs->fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl;
173
174 if (ctrl == EP_IN_DIRECTION_SET || ctrl == EP_ENABLE) {
175 idx = ((ep_idx - 4) % 3) + 1;
176 return &ext_ctrl[idx].epn_ext_ctrl1;
177 }
178
179 idx = (ep_idx - 4) / 2;
180 return &epn0n1_ext_ctrl[idx];
181 }
182
it82xx2_usb_extend_ep_ctrl(const struct device * dev,const uint8_t ep,const enum it82xx2_ep_ctrl ctrl,const bool enable)183 static int it82xx2_usb_extend_ep_ctrl(const struct device *dev, const uint8_t ep,
184 const enum it82xx2_ep_ctrl ctrl, const bool enable)
185 {
186 const struct usb_it82xx2_config *config = dev->config;
187 struct usb_it82xx2_regs *const usb_regs = config->base;
188 struct it82xx2_usb_ep_regs *ep_regs = usb_regs->usb_ep_regs;
189 struct epn_ext_ctrl_regs *ext_ctrl =
190 usb_regs->fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl;
191 volatile union epn_extend_ctrl1_reg *epn_ext_ctrl1 = NULL;
192 volatile union epn0n1_extend_ctrl_reg *epn0n1_ext_ctrl = NULL;
193 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
194 uint8_t fifo_idx = (ep_idx > 0) ? (ep_fifo_res[ep_idx % SHARED_FIFO_NUM]) : 0;
195
196 if (ctrl == EP_IN_DIRECTION_SET || ctrl == EP_ENABLE) {
197 epn_ext_ctrl1 = it82xx2_get_ext_ctrl(dev, ep_idx, ctrl);
198 } else {
199 epn0n1_ext_ctrl = it82xx2_get_ext_ctrl(dev, ep_idx, ctrl);
200 }
201
202 switch (ctrl) {
203 case EP_STALL_SEND:
204 if (ep_idx % 2) {
205 epn0n1_ext_ctrl->fields.epn1_send_stall_bit = enable;
206 } else {
207 epn0n1_ext_ctrl->fields.epn0_send_stall_bit = enable;
208 }
209 break;
210 case EP_IOS_ENABLE:
211 if (ep_idx % 2) {
212 epn0n1_ext_ctrl->fields.epn1_iso_enable_bit = enable;
213 } else {
214 epn0n1_ext_ctrl->fields.epn0_iso_enable_bit = enable;
215 }
216 break;
217 case EP_DATA_SEQ_1:
218 if (ep_idx % 2) {
219 epn0n1_ext_ctrl->fields.epn1_outdata_sequence_bit = enable;
220 } else {
221 epn0n1_ext_ctrl->fields.epn0_outdata_sequence_bit = enable;
222 }
223 break;
224 case EP_DATA_SEQ_TOGGLE:
225 if (!enable) {
226 break;
227 }
228 if (ep_idx % 2) {
229 if (epn0n1_ext_ctrl->fields.epn1_outdata_sequence_bit) {
230 epn0n1_ext_ctrl->fields.epn1_outdata_sequence_bit = 0;
231 } else {
232 epn0n1_ext_ctrl->fields.epn1_outdata_sequence_bit = 1;
233 }
234 } else {
235 if (epn0n1_ext_ctrl->fields.epn0_outdata_sequence_bit) {
236 epn0n1_ext_ctrl->fields.epn0_outdata_sequence_bit = 0;
237 } else {
238 epn0n1_ext_ctrl->fields.epn0_outdata_sequence_bit = 1;
239 }
240 }
241 break;
242 case EP_IN_DIRECTION_SET:
243 if (((ep_idx - 4) / 3 == 0)) {
244 epn_ext_ctrl1->fields.epn0_direction_bit = enable;
245 } else if (((ep_idx - 4) / 3 == 1)) {
246 epn_ext_ctrl1->fields.epn3_direction_bit = enable;
247 } else if (((ep_idx - 4) / 3 == 2)) {
248 epn_ext_ctrl1->fields.epn6_direction_bit = enable;
249 } else if (((ep_idx - 4) / 3 == 3)) {
250 epn_ext_ctrl1->fields.epn9_direction_bit = enable;
251 } else {
252 LOG_ERR("Invalid endpoint 0x%x for control type 0x%x", ep, ctrl);
253 return -EINVAL;
254 }
255 break;
256 case EP_ENABLE:
257 if (((ep_idx - 4) / 3 == 0)) {
258 epn_ext_ctrl1->fields.epn0_enable_bit = enable;
259 } else if (((ep_idx - 4) / 3 == 1)) {
260 epn_ext_ctrl1->fields.epn3_enable_bit = enable;
261 } else if (((ep_idx - 4) / 3 == 2)) {
262 epn_ext_ctrl1->fields.epn6_enable_bit = enable;
263 } else if (((ep_idx - 4) / 3 == 3)) {
264 epn_ext_ctrl1->fields.epn9_enable_bit = enable;
265 } else {
266 LOG_ERR("Invalid endpoint 0x%x for control type 0x%x", ep, ctrl);
267 return -EINVAL;
268 }
269 break;
270 case EP_READY_ENABLE:
271 int idx = ((ep_idx - 4) % 3) + 1;
272
273 (enable) ? (ext_ctrl[idx].epn_ext_ctrl2 |= BIT((ep_idx - 4) / 3))
274 : (ext_ctrl[idx].epn_ext_ctrl2 &= ~BIT((ep_idx - 4) / 3));
275 ep_regs[fifo_idx].ep_ctrl.fields.ready_bit = enable;
276 break;
277 default:
278 LOG_ERR("Unknown control type 0x%x", ctrl);
279 return -EINVAL;
280 }
281
282 return 0;
283 }
284
it82xx2_usb_ep_ctrl(const struct device * dev,uint8_t ep,enum it82xx2_ep_ctrl ctrl,bool enable)285 static int it82xx2_usb_ep_ctrl(const struct device *dev, uint8_t ep, enum it82xx2_ep_ctrl ctrl,
286 bool enable)
287 {
288 const struct usb_it82xx2_config *config = dev->config;
289 struct usb_it82xx2_regs *const usb_regs = config->base;
290 struct it82xx2_usb_ep_regs *ep_regs = usb_regs->usb_ep_regs;
291 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
292 uint8_t ep_ctrl_value;
293
294 if (IT8XXX2_IS_EXTEND_ENDPOINT(ep_idx)) {
295 return -EINVAL;
296 }
297
298 ep_ctrl_value = ep_regs[ep_idx].ep_ctrl.value & ~ENDPOINT_READY_BIT;
299
300 switch (ctrl) {
301 case EP_STALL_SEND:
302 if (enable) {
303 ep_ctrl_value |= ENDPOINT_SEND_STALL_BIT;
304 } else {
305 ep_ctrl_value &= ~ENDPOINT_SEND_STALL_BIT;
306 }
307 break;
308 case EP_IN_DIRECTION_SET:
309 if (enable) {
310 ep_ctrl_value |= ENDPOINT_DIRECTION_BIT;
311 } else {
312 ep_ctrl_value &= ~ENDPOINT_DIRECTION_BIT;
313 }
314 break;
315 case EP_IOS_ENABLE:
316 if (enable) {
317 ep_ctrl_value |= ENDPOINT_ISO_ENABLE_BIT;
318 } else {
319 ep_ctrl_value &= ~ENDPOINT_ISO_ENABLE_BIT;
320 }
321 break;
322 case EP_ENABLE:
323 if (enable) {
324 ep_ctrl_value |= ENDPOINT_ENABLE_BIT;
325 } else {
326 ep_ctrl_value &= ~ENDPOINT_ENABLE_BIT;
327 }
328 break;
329 case EP_READY_ENABLE:
330 if (enable) {
331 ep_ctrl_value |= ENDPOINT_READY_BIT;
332 } else {
333 ep_ctrl_value &= ~ENDPOINT_READY_BIT;
334 }
335 break;
336 case EP_DATA_SEQ_1:
337 if (enable) {
338 ep_ctrl_value |= ENDPOINT_OUTDATA_SEQ_BIT;
339 } else {
340 ep_ctrl_value &= ~ENDPOINT_OUTDATA_SEQ_BIT;
341 }
342 break;
343 case EP_DATA_SEQ_TOGGLE:
344 if (!enable) {
345 break;
346 }
347 ep_ctrl_value ^= ENDPOINT_OUTDATA_SEQ_BIT;
348 break;
349 default:
350 LOG_ERR("Unknown control type 0x%x", ctrl);
351 return -EINVAL;
352 }
353
354 ep_regs[ep_idx].ep_ctrl.value = ep_ctrl_value;
355 return 0;
356 }
357
it82xx2_usb_set_ep_ctrl(const struct device * dev,uint8_t ep,enum it82xx2_ep_ctrl ctrl,bool enable)358 static int it82xx2_usb_set_ep_ctrl(const struct device *dev, uint8_t ep, enum it82xx2_ep_ctrl ctrl,
359 bool enable)
360 {
361 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
362 int ret = 0;
363 unsigned int key;
364
365 key = irq_lock();
366 if (IT8XXX2_IS_EXTEND_ENDPOINT(ep_idx)) {
367 ret = it82xx2_usb_extend_ep_ctrl(dev, ep, ctrl, enable);
368 } else {
369 ret = it82xx2_usb_ep_ctrl(dev, ep, ctrl, enable);
370 }
371 irq_unlock(key);
372 return ret;
373 }
374
375 /* Standby(deep doze) mode enable/disable */
it82xx2_enable_standby_state(bool enable)376 static void it82xx2_enable_standby_state(bool enable)
377 {
378 if (enable) {
379 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
380 } else {
381 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
382 }
383 }
384
385 /* Wake-up interrupt (USB D+) Enable/Disable */
it82xx2_enable_wu_irq(const struct device * dev,bool enable)386 static void it82xx2_enable_wu_irq(const struct device *dev, bool enable)
387 {
388 const struct usb_it82xx2_config *config = dev->config;
389
390 /* Clear pending interrupt */
391 it8xxx2_wuc_clear_status(config->wuc.dev, config->wuc.mask);
392
393 if (enable) {
394 irq_enable(config->wu_irq);
395 } else {
396 irq_disable(config->wu_irq);
397 }
398 }
399
it82xx2_wu_isr(const void * arg)400 static void it82xx2_wu_isr(const void *arg)
401 {
402 const struct device *dev = arg;
403
404 it82xx2_enable_wu_irq(dev, false);
405 it82xx2_enable_standby_state(false);
406 LOG_DBG("USB D+ (WU) Triggered");
407 }
408
it8xxx2_usb_dc_wuc_init(const struct device * dev)409 static void it8xxx2_usb_dc_wuc_init(const struct device *dev)
410 {
411 const struct usb_it82xx2_config *config = dev->config;
412
413 /* Initializing the WUI */
414 it8xxx2_wuc_set_polarity(config->wuc.dev, config->wuc.mask, WUC_TYPE_EDGE_FALLING);
415 it8xxx2_wuc_clear_status(config->wuc.dev, config->wuc.mask);
416
417 /* Enabling the WUI */
418 it8xxx2_wuc_enable(config->wuc.dev, config->wuc.mask);
419
420 /* Connect WU (USB D+) interrupt but make it disabled initially */
421 irq_connect_dynamic(config->wu_irq, 0, it82xx2_wu_isr, dev, 0);
422 }
423
it82xx2_usb_fifo_ctrl(const struct device * dev,const uint8_t ep,const bool reset)424 static int it82xx2_usb_fifo_ctrl(const struct device *dev, const uint8_t ep, const bool reset)
425 {
426 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
427 const struct usb_it82xx2_config *config = dev->config;
428 struct usb_it82xx2_regs *const usb_regs = config->base;
429 volatile uint8_t *ep_fifo_ctrl = usb_regs->fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl;
430 uint8_t fifon_ctrl = (ep_fifo_res[ep_idx % SHARED_FIFO_NUM] - 1) * 2;
431 unsigned int key;
432 int ret = 0;
433
434 if (ep_idx == 0) {
435 LOG_ERR("Invalid endpoint 0x%x", ep);
436 return -EINVAL;
437 }
438
439 key = irq_lock();
440 if (reset) {
441 ep_fifo_ctrl[fifon_ctrl] = 0x0;
442 ep_fifo_ctrl[fifon_ctrl + 1] = 0x0;
443 irq_unlock(key);
444 return 0;
445 }
446
447 if (USB_EP_DIR_IS_IN(ep)) {
448 if (ep_idx < 8) {
449 ep_fifo_ctrl[fifon_ctrl] = BIT(ep_idx);
450 ep_fifo_ctrl[fifon_ctrl + 1] = 0x0;
451 } else {
452 ep_fifo_ctrl[fifon_ctrl] = 0x0;
453 ep_fifo_ctrl[fifon_ctrl + 1] = BIT(ep_idx - 8);
454 }
455 } else if (USB_EP_DIR_IS_OUT(ep)) {
456 if (ep_idx < 8) {
457 ep_fifo_ctrl[fifon_ctrl] |= BIT(ep_idx);
458 } else {
459 ep_fifo_ctrl[fifon_ctrl + 1] |= BIT(ep_idx - 8);
460 }
461 } else {
462 LOG_ERR("Failed to set fifo control register for ep 0x%x", ep);
463 ret = -EINVAL;
464 }
465 irq_unlock(key);
466
467 return ret;
468 }
469
it82xx2_event_submit(const struct device * dev,const uint8_t ep,const enum it82xx2_event_type event)470 static void it82xx2_event_submit(const struct device *dev, const uint8_t ep,
471 const enum it82xx2_event_type event)
472 {
473 struct it82xx2_ep_event evt;
474
475 evt.dev = dev;
476 evt.ep = ep;
477 evt.event = event;
478 k_msgq_put(&evt_msgq, &evt, K_NO_WAIT);
479 }
480
it82xx2_ep_enqueue(const struct device * dev,struct udc_ep_config * const cfg,struct net_buf * const buf)481 static int it82xx2_ep_enqueue(const struct device *dev, struct udc_ep_config *const cfg,
482 struct net_buf *const buf)
483 {
484 udc_buf_put(cfg, buf);
485
486 it82xx2_event_submit(dev, cfg->addr, IT82xx2_EVT_XFER);
487 return 0;
488 }
489
it82xx2_ep_dequeue(const struct device * dev,struct udc_ep_config * const cfg)490 static int it82xx2_ep_dequeue(const struct device *dev, struct udc_ep_config *const cfg)
491 {
492 const uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
493 const struct usb_it82xx2_config *config = dev->config;
494 struct usb_it82xx2_regs *const usb_regs = config->base;
495 struct it82xx2_usb_ep_fifo_regs *ff_regs = usb_regs->fifo_regs;
496 struct net_buf *buf;
497 unsigned int lock_key;
498 uint8_t fifo_idx;
499
500 fifo_idx = ep_idx > 0 ? ep_fifo_res[ep_idx % SHARED_FIFO_NUM] : 0;
501 lock_key = irq_lock();
502 if (USB_EP_DIR_IS_IN(cfg->addr)) {
503 ff_regs[fifo_idx].ep_tx_fifo_ctrl = FIFO_FORCE_EMPTY;
504 } else {
505 ff_regs[fifo_idx].ep_rx_fifo_ctrl = FIFO_FORCE_EMPTY;
506 }
507 irq_unlock(lock_key);
508
509 buf = udc_buf_get_all(dev, cfg->addr);
510 if (buf) {
511 udc_submit_ep_event(dev, buf, -ECONNABORTED);
512 }
513
514 udc_ep_set_busy(dev, cfg->addr, false);
515
516 return 0;
517 }
518
ctrl_ep_stall_workaround(const struct device * dev)519 static inline void ctrl_ep_stall_workaround(const struct device *dev)
520 {
521 const struct usb_it82xx2_config *config = dev->config;
522 struct usb_it82xx2_regs *const usb_regs = config->base;
523 struct it82xx2_usb_ep_regs *ep_regs = usb_regs->usb_ep_regs;
524 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
525 struct it82xx2_data *priv = udc_get_private(dev);
526 unsigned int lock_key;
527 uint32_t idx = 0;
528
529 priv->stall_is_sent = true;
530 lock_key = irq_lock();
531 it82xx2_usb_set_ep_ctrl(dev, 0, EP_STALL_SEND, true);
532 it82xx2_usb_set_ep_ctrl(dev, 0, EP_READY_ENABLE, true);
533
534 /* It82xx2 does not support clearing the STALL bit by hardware; instead, the STALL bit need
535 * to be cleared by firmware. The SETUP token will be STALLed, which isn't compliant to
536 * USB specification, if firmware clears the STALL bit too late. Due to this hardware
537 * limitations, device controller polls to check if the stall bit has been transmitted for
538 * 3ms and then disables it after responsing STALLed.
539 */
540 while (idx < 198 && !(ep_regs[0].ep_status & DC_STALL_SENT)) {
541 /* wait 15.15us */
542 gctrl_regs->GCTRL_WNCKR = 0;
543 idx++;
544 }
545
546 if (idx < 198) {
547 it82xx2_usb_set_ep_ctrl(dev, 0, EP_STALL_SEND, false);
548 }
549 irq_unlock(lock_key);
550 }
551
it82xx2_ep_set_halt(const struct device * dev,struct udc_ep_config * const cfg)552 static int it82xx2_ep_set_halt(const struct device *dev, struct udc_ep_config *const cfg)
553 {
554 const uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
555
556 if (ep_idx == 0) {
557 ctrl_ep_stall_workaround(dev);
558 } else {
559 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_STALL_SEND, true);
560 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_READY_ENABLE, true);
561 }
562
563 LOG_DBG("Endpoint 0x%x is halted", cfg->addr);
564
565 return 0;
566 }
567
it82xx2_ep_clear_halt(const struct device * dev,struct udc_ep_config * const cfg)568 static int it82xx2_ep_clear_halt(const struct device *dev, struct udc_ep_config *const cfg)
569 {
570 const uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
571
572 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_STALL_SEND, false);
573
574 LOG_DBG("Endpoint 0x%x clear halted", cfg->addr);
575
576 return 0;
577 }
578
it82xx2_ep_enable(const struct device * dev,struct udc_ep_config * const cfg)579 static int it82xx2_ep_enable(const struct device *dev, struct udc_ep_config *const cfg)
580 {
581 const uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
582
583 /* Configure endpoint */
584 if (ep_idx != 0) {
585 if (USB_EP_DIR_IS_IN(cfg->addr)) {
586 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_DATA_SEQ_1, false);
587 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_IN_DIRECTION_SET, true);
588 /* clear fifo control registers */
589 it82xx2_usb_fifo_ctrl(dev, cfg->addr, true);
590 } else {
591 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_IN_DIRECTION_SET, false);
592 it82xx2_usb_fifo_ctrl(dev, cfg->addr, false);
593 }
594
595 switch (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) {
596 case USB_EP_TYPE_BULK:
597 __fallthrough;
598 case USB_EP_TYPE_INTERRUPT:
599 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_IOS_ENABLE, false);
600 break;
601 case USB_EP_TYPE_ISO:
602 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_IOS_ENABLE, true);
603 break;
604 case USB_EP_TYPE_CONTROL:
605 __fallthrough;
606 default:
607 return -ENOTSUP;
608 }
609 }
610
611 if (IT8XXX2_IS_EXTEND_ENDPOINT(ep_idx)) {
612 uint8_t fifo_idx;
613
614 fifo_idx = ep_fifo_res[ep_idx % SHARED_FIFO_NUM];
615 it82xx2_usb_set_ep_ctrl(dev, fifo_idx, EP_ENABLE, true);
616 }
617
618 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_ENABLE, true);
619
620 LOG_DBG("Endpoint 0x%02x is enabled", cfg->addr);
621
622 return 0;
623 }
624
it82xx2_ep_disable(const struct device * dev,struct udc_ep_config * const cfg)625 static int it82xx2_ep_disable(const struct device *dev, struct udc_ep_config *const cfg)
626 {
627 const uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
628
629 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_ENABLE, false);
630
631 LOG_DBG("Endpoint 0x%02x is disabled", cfg->addr);
632
633 return 0;
634 }
635
it82xx2_host_wakeup(const struct device * dev)636 static int it82xx2_host_wakeup(const struct device *dev)
637 {
638 struct it82xx2_data *priv = udc_get_private(dev);
639 const struct usb_it82xx2_config *config = dev->config;
640 struct usb_it82xx2_regs *const usb_regs = config->base;
641 int ret = -EACCES;
642
643 if (udc_is_suspended(dev)) {
644 usb_regs->dc_control = DC_GLOBAL_ENABLE | DC_FULL_SPEED_LINE_POLARITY |
645 DC_FULL_SPEED_LINE_RATE | DC_DIRECT_CONTROL |
646 DC_TX_LINE_STATE_DM | DC_CONNECT_TO_HOST;
647
648 /* The remote wakeup device must hold the resume signal for */
649 /* at least 1 ms but for no more than 15 ms */
650 k_msleep(2);
651
652 usb_regs->dc_control = DC_GLOBAL_ENABLE | DC_FULL_SPEED_LINE_POLARITY |
653 DC_FULL_SPEED_LINE_RATE | DC_CONNECT_TO_HOST;
654
655 ret = k_sem_take(&priv->suspended_sem, K_MSEC(500));
656 if (ret < 0) {
657 LOG_ERR("Failed to wake up host");
658 }
659 }
660
661 return ret;
662 }
663
it82xx2_set_address(const struct device * dev,const uint8_t addr)664 static int it82xx2_set_address(const struct device *dev, const uint8_t addr)
665 {
666 const struct usb_it82xx2_config *config = dev->config;
667 struct usb_it82xx2_regs *const usb_regs = config->base;
668
669 usb_regs->dc_address = addr & DC_ADDR_MASK;
670
671 LOG_DBG("Set usb address 0x%02x", addr);
672
673 return 0;
674 }
675
it82xx2_usb_dc_ip_init(const struct device * dev)676 static int it82xx2_usb_dc_ip_init(const struct device *dev)
677 {
678 const struct usb_it82xx2_config *config = dev->config;
679 struct usb_it82xx2_regs *const usb_regs = config->base;
680
681 /* reset usb controller */
682 usb_regs->host_device_control = RESET_CORE;
683 k_msleep(1);
684 usb_regs->port0_misc_control &= ~(PULL_DOWN_EN);
685 usb_regs->port1_misc_control &= ~(PULL_DOWN_EN);
686
687 /* clear reset bit */
688 usb_regs->host_device_control = 0;
689
690 usb_regs->dc_interrupt_status =
691 DC_TRANS_DONE | DC_RESET_EVENT | DC_SOF_RECEIVED | DC_RESUME_EVENT;
692
693 usb_regs->dc_interrupt_mask = 0x00;
694 usb_regs->dc_interrupt_mask =
695 DC_TRANS_DONE | DC_RESET_EVENT | DC_SOF_RECEIVED | DC_RESUME_EVENT;
696
697 usb_regs->dc_address = DC_ADDR_NULL;
698
699 return 0;
700 }
701
it82xx2_enable_resume_int(const struct device * dev,bool enable)702 static void it82xx2_enable_resume_int(const struct device *dev, bool enable)
703 {
704 const struct usb_it82xx2_config *config = dev->config;
705 struct usb_it82xx2_regs *const usb_regs = config->base;
706
707 usb_regs->dc_interrupt_status = DC_RESUME_EVENT;
708 if (enable) {
709 usb_regs->dc_interrupt_mask |= DC_RESUME_EVENT;
710 } else {
711 usb_regs->dc_interrupt_mask &= ~DC_RESUME_EVENT;
712 }
713 }
714
it82xx2_enable_sof_int(const struct device * dev,bool enable)715 static void it82xx2_enable_sof_int(const struct device *dev, bool enable)
716 {
717 const struct usb_it82xx2_config *config = dev->config;
718 struct usb_it82xx2_regs *const usb_regs = config->base;
719
720 usb_regs->dc_interrupt_status = DC_SOF_RECEIVED;
721 if (enable) {
722 usb_regs->dc_interrupt_mask |= DC_SOF_RECEIVED;
723 } else {
724 usb_regs->dc_interrupt_mask &= ~DC_SOF_RECEIVED;
725 }
726 }
727
it82xx2_dc_reset(const struct device * dev)728 void it82xx2_dc_reset(const struct device *dev)
729 {
730 const struct usb_it82xx2_config *config = dev->config;
731 struct usb_it82xx2_regs *const usb_regs = config->base;
732 struct it82xx2_usb_ep_regs *ep_regs = usb_regs->usb_ep_regs;
733 struct it82xx2_usb_ep_fifo_regs *ff_regs = usb_regs->fifo_regs;
734 struct it82xx2_data *priv = udc_get_private(dev);
735
736 for (uint8_t ep_idx = 0; ep_idx < 4; ep_idx++) {
737 ff_regs[ep_idx].ep_rx_fifo_ctrl = FIFO_FORCE_EMPTY;
738 ff_regs[ep_idx].ep_tx_fifo_ctrl = FIFO_FORCE_EMPTY;
739 }
740
741 ep_regs[0].ep_ctrl.value = ENDPOINT_EN;
742 usb_regs->dc_address = DC_ADDR_NULL;
743 usb_regs->dc_interrupt_status = DC_NAK_SENT_INT | DC_SOF_RECEIVED;
744
745 atomic_clear_bit(&priv->out_fifo_state, IT82xx2_STATE_OUT_SHARED_FIFO_BUSY);
746
747 k_sem_give(&priv->fifo_sem[0]);
748 k_sem_give(&priv->fifo_sem[1]);
749 k_sem_give(&priv->fifo_sem[2]);
750 }
751
it82xx2_xfer_in_data(const struct device * dev,uint8_t ep,struct net_buf * buf)752 static int it82xx2_xfer_in_data(const struct device *dev, uint8_t ep, struct net_buf *buf)
753 {
754 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
755 const struct usb_it82xx2_config *config = dev->config;
756 struct usb_it82xx2_regs *const usb_regs = config->base;
757 struct it82xx2_usb_ep_fifo_regs *ff_regs = usb_regs->fifo_regs;
758 struct it82xx2_data *priv = udc_get_private(dev);
759 struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep);
760 unsigned int key;
761 uint8_t fifo_idx;
762 size_t len;
763
764 fifo_idx = ep_idx > 0 ? ep_fifo_res[ep_idx % SHARED_FIFO_NUM] : 0;
765 if (ep_idx == 0) {
766 ff_regs[ep_idx].ep_tx_fifo_ctrl = FIFO_FORCE_EMPTY;
767 } else {
768 k_sem_take(&priv->fifo_sem[fifo_idx - 1], K_FOREVER);
769 key = irq_lock();
770 it82xx2_usb_fifo_ctrl(dev, ep, false);
771 }
772
773 len = MIN(buf->len, udc_mps_ep_size(ep_cfg));
774
775 for (size_t i = 0; i < len; i++) {
776 ff_regs[fifo_idx].ep_tx_fifo_data = buf->data[i];
777 }
778
779 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_READY_ENABLE, true);
780 if (ep_idx != 0) {
781 irq_unlock(key);
782 }
783
784 LOG_DBG("Writed %d packets to endpoint%d tx fifo", buf->len, ep_idx);
785
786 return 0;
787 }
788
it82xx2_xfer_out_data(const struct device * dev,uint8_t ep,struct net_buf * buf)789 static int it82xx2_xfer_out_data(const struct device *dev, uint8_t ep, struct net_buf *buf)
790 {
791 const struct usb_it82xx2_config *config = dev->config;
792 struct usb_it82xx2_regs *const usb_regs = config->base;
793 struct it82xx2_usb_ep_regs *ep_regs = usb_regs->usb_ep_regs;
794 struct it82xx2_usb_ep_fifo_regs *ff_regs = usb_regs->fifo_regs;
795 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
796 uint8_t fifo_idx;
797 size_t len;
798
799 fifo_idx = ep_idx > 0 ? ep_fifo_res[ep_idx % SHARED_FIFO_NUM] : 0;
800 if (ep_regs[fifo_idx].ep_status & EP_STATUS_ERROR) {
801 LOG_WRN("endpoint%d error status 0x%02x", ep_idx, ep_regs[fifo_idx].ep_status);
802 return -EINVAL;
803 }
804
805 len = (uint16_t)ff_regs[fifo_idx].ep_rx_fifo_dcnt_lsb +
806 (((uint16_t)ff_regs[fifo_idx].ep_rx_fifo_dcnt_msb) << 8);
807
808 len = MIN(net_buf_tailroom(buf), len);
809 uint8_t *data_ptr = net_buf_tail(buf);
810
811 for (size_t idx = 0; idx < len; idx++) {
812 data_ptr[idx] = ff_regs[fifo_idx].ep_rx_fifo_data;
813 }
814
815 net_buf_add(buf, len);
816
817 return 0;
818 }
819
get_fifo_ctrl(const struct device * dev,const uint8_t fifo_idx)820 static uint16_t get_fifo_ctrl(const struct device *dev, const uint8_t fifo_idx)
821 {
822 const struct usb_it82xx2_config *config = dev->config;
823 struct usb_it82xx2_regs *const usb_regs = config->base;
824 volatile uint8_t *ep_fifo_ctrl = usb_regs->fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl;
825 uint8_t fifon_ctrl;
826
827 if (fifo_idx == 0) {
828 LOG_ERR("Invalid fifo_idx 0x%x", fifo_idx);
829 return 0;
830 }
831
832 fifon_ctrl = (fifo_idx - 1) * 2;
833
834 return (ep_fifo_ctrl[fifon_ctrl + 1] << 8 | ep_fifo_ctrl[fifon_ctrl]);
835 }
836
work_handler_xfer_continue(const struct device * dev,uint8_t ep,struct net_buf * buf)837 static int work_handler_xfer_continue(const struct device *dev, uint8_t ep, struct net_buf *buf)
838 {
839 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
840 int ret = 0;
841 uint8_t fifo_idx;
842
843 fifo_idx = ep_idx > 0 ? ep_fifo_res[ep_idx % SHARED_FIFO_NUM] : 0;
844 if (USB_EP_DIR_IS_OUT(ep)) {
845 unsigned int key;
846
847 if (ep_idx != 0) {
848 struct it82xx2_data *priv = udc_get_private(dev);
849
850 key = irq_lock();
851 atomic_set_bit(&priv->out_fifo_state, IT82xx2_STATE_OUT_SHARED_FIFO_BUSY);
852 }
853 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_READY_ENABLE, true);
854 if (ep_idx != 0) {
855 irq_unlock(key);
856 }
857 } else {
858 ret = it82xx2_xfer_in_data(dev, ep, buf);
859 }
860
861 return ret;
862 }
863
work_handler_xfer_next(const struct device * dev,uint8_t ep)864 static int work_handler_xfer_next(const struct device *dev, uint8_t ep)
865 {
866 struct net_buf *buf;
867
868 buf = udc_buf_peek(dev, ep);
869 if (buf == NULL) {
870 return -ENODATA;
871 }
872
873 return work_handler_xfer_continue(dev, ep, buf);
874 }
875
876 /*
877 * Allocate buffer and initiate a new control OUT transfer,
878 * use successive buffer descriptor when next is true.
879 */
it82xx2_ctrl_feed_dout(const struct device * dev,const size_t length)880 static int it82xx2_ctrl_feed_dout(const struct device *dev, const size_t length)
881 {
882 struct udc_ep_config *cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
883 struct net_buf *buf;
884
885 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, length);
886 if (buf == NULL) {
887 return -ENOMEM;
888 }
889 udc_buf_put(cfg, buf);
890
891 it82xx2_usb_set_ep_ctrl(dev, 0, EP_READY_ENABLE, true);
892
893 return 0;
894 }
895
get_extend_enable_bit(const struct device * dev,const uint8_t ep_idx)896 static bool get_extend_enable_bit(const struct device *dev, const uint8_t ep_idx)
897 {
898 union epn_extend_ctrl1_reg *epn_ext_ctrl1 = NULL;
899 bool enable;
900
901 epn_ext_ctrl1 = (union epn_extend_ctrl1_reg *)it82xx2_get_ext_ctrl(dev, ep_idx, EP_ENABLE);
902 if (((ep_idx - 4) / 3 == 0)) {
903 enable = (epn_ext_ctrl1->fields.epn0_enable_bit != 0);
904 } else if (((ep_idx - 4) / 3 == 1)) {
905 enable = (epn_ext_ctrl1->fields.epn3_enable_bit != 0);
906 } else if (((ep_idx - 4) / 3 == 2)) {
907 enable = (epn_ext_ctrl1->fields.epn6_enable_bit != 0);
908 } else {
909 enable = (epn_ext_ctrl1->fields.epn9_enable_bit != 0);
910 }
911 return enable;
912 }
913
get_extend_ready_bit(const struct device * dev,const uint8_t ep_idx)914 static bool get_extend_ready_bit(const struct device *dev, const uint8_t ep_idx)
915 {
916 const struct usb_it82xx2_config *config = dev->config;
917 struct usb_it82xx2_regs *const usb_regs = config->base;
918 struct epn_ext_ctrl_regs *ext_ctrl =
919 usb_regs->fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl;
920 int idx = ((ep_idx - 4) % 3) + 1;
921
922 return ((ext_ctrl[idx].epn_ext_ctrl2 & BIT((ep_idx - 4) / 3)) != 0);
923 }
924
it82xx2_fake_token(const struct device * dev,const uint8_t ep,const uint8_t token_type)925 static bool it82xx2_fake_token(const struct device *dev, const uint8_t ep, const uint8_t token_type)
926 {
927 struct it82xx2_data *priv = udc_get_private(dev);
928 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
929 uint8_t fifo_idx;
930 bool is_fake = false;
931
932 fifo_idx = ep_idx > 0 ? ep_fifo_res[ep_idx % SHARED_FIFO_NUM] : 0;
933
934 switch (token_type) {
935 case DC_IN_TRANS:
936 if (ep_idx == 0) {
937 if (priv->stall_is_sent) {
938 return true;
939 }
940 is_fake = !udc_ctrl_stage_is_data_in(dev) &&
941 !udc_ctrl_stage_is_status_in(dev) &&
942 !udc_ctrl_stage_is_no_data(dev);
943 } else {
944 if (get_fifo_ctrl(dev, fifo_idx) != BIT(ep_idx)) {
945 is_fake = true;
946 }
947 }
948 break;
949 case DC_OUTDATA_TRANS:
950 if (ep_idx == 0) {
951 is_fake = !udc_ctrl_stage_is_data_out(dev) &&
952 !udc_ctrl_stage_is_status_out(dev);
953 } else {
954 if (!atomic_test_bit(&priv->out_fifo_state,
955 IT82xx2_STATE_OUT_SHARED_FIFO_BUSY)) {
956 is_fake = true;
957 }
958 }
959 break;
960 default:
961 LOG_ERR("Invalid token type(%d)", token_type);
962 is_fake = true;
963 break;
964 }
965
966 return is_fake;
967 }
968
work_handler_in(const struct device * dev,uint8_t ep)969 static inline int work_handler_in(const struct device *dev, uint8_t ep)
970 {
971 struct it82xx2_data *priv = udc_get_private(dev);
972 struct udc_ep_config *ep_cfg;
973 struct net_buf *buf;
974 uint8_t fifo_idx;
975 int err = 0;
976
977 if (it82xx2_fake_token(dev, ep, DC_IN_TRANS)) {
978 return 0;
979 }
980
981 if (ep != USB_CONTROL_EP_IN) {
982 fifo_idx = ep_fifo_res[USB_EP_GET_IDX(ep) % SHARED_FIFO_NUM];
983 it82xx2_usb_fifo_ctrl(dev, ep, true);
984 k_sem_give(&priv->fifo_sem[fifo_idx - 1]);
985 }
986
987 buf = udc_buf_peek(dev, ep);
988 if (buf == NULL) {
989 return -ENODATA;
990 }
991 ep_cfg = udc_get_ep_cfg(dev, ep);
992
993 net_buf_pull(buf, MIN(buf->len, udc_mps_ep_size(ep_cfg)));
994
995 it82xx2_usb_set_ep_ctrl(dev, ep, EP_DATA_SEQ_TOGGLE, true);
996
997 if (buf->len) {
998 work_handler_xfer_continue(dev, ep, buf);
999 return 0;
1000 }
1001
1002 if (udc_ep_buf_has_zlp(buf)) {
1003 work_handler_xfer_continue(dev, ep, buf);
1004 udc_ep_buf_clear_zlp(buf);
1005 return 0;
1006 }
1007
1008 buf = udc_buf_get(dev, ep);
1009 if (buf == NULL) {
1010 return -ENODATA;
1011 }
1012
1013 udc_ep_set_busy(dev, ep, false);
1014
1015 if (ep == USB_CONTROL_EP_IN) {
1016 if (udc_ctrl_stage_is_status_in(dev) || udc_ctrl_stage_is_no_data(dev)) {
1017 /* Status stage finished, notify upper layer */
1018 udc_ctrl_submit_status(dev, buf);
1019 }
1020
1021 /* Update to next stage of control transfer */
1022 udc_ctrl_update_stage(dev, buf);
1023
1024 if (udc_ctrl_stage_is_status_out(dev)) {
1025 /*
1026 * IN transfer finished, release buffer,
1027 * Feed control OUT buffer for status stage.
1028 */
1029 net_buf_unref(buf);
1030 err = it82xx2_ctrl_feed_dout(dev, 0U);
1031 }
1032 return err;
1033 }
1034
1035 return udc_submit_ep_event(dev, buf, 0);
1036 }
1037
work_handler_setup(const struct device * dev,uint8_t ep)1038 static inline int work_handler_setup(const struct device *dev, uint8_t ep)
1039 {
1040 struct it82xx2_data *priv = udc_get_private(dev);
1041 struct net_buf *buf;
1042 int err = 0;
1043
1044 if (udc_ctrl_stage_is_status_out(dev)) {
1045 /* out -> setup */
1046 buf = udc_buf_get(dev, USB_CONTROL_EP_OUT);
1047 if (buf) {
1048 udc_ep_set_busy(dev, USB_CONTROL_EP_OUT, false);
1049 net_buf_unref(buf);
1050 }
1051 }
1052
1053 if (udc_ctrl_stage_is_status_in(dev) || udc_ctrl_stage_is_no_data(dev)) {
1054 /* in -> setup */
1055 work_handler_in(dev, USB_CONTROL_EP_IN);
1056 }
1057
1058 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, sizeof(struct usb_setup_packet));
1059 if (buf == NULL) {
1060 LOG_ERR("Failed to allocate buffer");
1061 return -ENOMEM;
1062 }
1063
1064 udc_ep_buf_set_setup(buf);
1065 it82xx2_xfer_out_data(dev, ep, buf);
1066 if (buf->len != sizeof(struct usb_setup_packet)) {
1067 LOG_DBG("buffer length %d read from chip", buf->len);
1068 net_buf_unref(buf);
1069 return 0;
1070 }
1071
1072 priv->stall_is_sent = false;
1073 LOG_HEXDUMP_DBG(buf->data, buf->len, "setup:");
1074
1075 udc_ctrl_update_stage(dev, buf);
1076
1077 it82xx2_usb_set_ep_ctrl(dev, ep, EP_DATA_SEQ_1, true);
1078
1079 if (udc_ctrl_stage_is_data_out(dev)) {
1080 /* Allocate and feed buffer for data OUT stage */
1081 LOG_DBG("s:%p|feed for -out-", buf);
1082 err = it82xx2_ctrl_feed_dout(dev, udc_data_stage_length(buf));
1083 if (err == -ENOMEM) {
1084 err = udc_submit_ep_event(dev, buf, err);
1085 }
1086 } else if (udc_ctrl_stage_is_data_in(dev)) {
1087 udc_ctrl_submit_s_in_status(dev);
1088 } else {
1089 udc_ctrl_submit_s_status(dev);
1090 }
1091
1092 return err;
1093 }
1094
work_handler_out(const struct device * dev,uint8_t ep)1095 static inline int work_handler_out(const struct device *dev, uint8_t ep)
1096 {
1097 struct net_buf *buf;
1098 int err = 0;
1099 const uint8_t ep_idx = USB_EP_GET_IDX(ep);
1100 const struct usb_it82xx2_config *config = dev->config;
1101 struct it82xx2_data *priv = udc_get_private(dev);
1102 struct usb_it82xx2_regs *const usb_regs = config->base;
1103 struct it82xx2_usb_ep_fifo_regs *ff_regs = usb_regs->fifo_regs;
1104 struct udc_ep_config *ep_cfg;
1105 uint8_t fifo_idx;
1106 size_t len;
1107
1108 if (it82xx2_fake_token(dev, ep, DC_OUTDATA_TRANS)) {
1109 return 0;
1110 }
1111
1112 buf = udc_buf_peek(dev, ep);
1113 if (buf == NULL) {
1114 return -ENODATA;
1115 }
1116
1117 fifo_idx = ep_idx > 0 ? ep_fifo_res[ep_idx % SHARED_FIFO_NUM] : 0;
1118 len = (uint16_t)ff_regs[fifo_idx].ep_rx_fifo_dcnt_lsb +
1119 (((uint16_t)ff_regs[fifo_idx].ep_rx_fifo_dcnt_msb) << 8);
1120
1121 if (ep == USB_CONTROL_EP_OUT) {
1122 if (udc_ctrl_stage_is_status_out(dev) && len != 0) {
1123 LOG_DBG("Handle early setup token");
1124 buf = udc_buf_get(dev, ep);
1125 /* Notify upper layer */
1126 udc_ctrl_submit_status(dev, buf);
1127 /* Update to next stage of control transfer */
1128 udc_ctrl_update_stage(dev, buf);
1129 return 0;
1130 }
1131 }
1132
1133 ep_cfg = udc_get_ep_cfg(dev, ep);
1134 if (len > udc_mps_ep_size(ep_cfg)) {
1135 LOG_ERR("Failed to handle this packet due to the packet size");
1136 return -ENOBUFS;
1137 }
1138
1139 it82xx2_xfer_out_data(dev, ep, buf);
1140
1141 LOG_DBG("Handle data OUT, %zu | %zu", len, net_buf_tailroom(buf));
1142
1143 if (net_buf_tailroom(buf) && len == udc_mps_ep_size(ep_cfg)) {
1144 work_handler_xfer_continue(dev, ep, buf);
1145 if (ep != USB_CONTROL_EP_OUT) {
1146 err = udc_submit_ep_event(dev, buf, 0);
1147 }
1148 return err;
1149 }
1150
1151 buf = udc_buf_get(dev, ep);
1152 if (buf == NULL) {
1153 return -ENODATA;
1154 }
1155
1156 udc_ep_set_busy(dev, ep, false);
1157
1158 if (ep == USB_CONTROL_EP_OUT) {
1159 if (udc_ctrl_stage_is_status_out(dev)) {
1160 /* Status stage finished, notify upper layer */
1161 udc_ctrl_submit_status(dev, buf);
1162 }
1163
1164 /* Update to next stage of control transfer */
1165 udc_ctrl_update_stage(dev, buf);
1166
1167 if (udc_ctrl_stage_is_status_in(dev)) {
1168 it82xx2_usb_set_ep_ctrl(dev, ep, EP_DATA_SEQ_1, true);
1169 err = udc_ctrl_submit_s_out_status(dev, buf);
1170 }
1171 } else {
1172 atomic_clear_bit(&priv->out_fifo_state, IT82xx2_STATE_OUT_SHARED_FIFO_BUSY);
1173 err = udc_submit_ep_event(dev, buf, 0);
1174 }
1175
1176 return err;
1177 }
1178
xfer_work_handler(const struct device * dev)1179 static void xfer_work_handler(const struct device *dev)
1180 {
1181 while (true) {
1182 struct it82xx2_ep_event evt;
1183 int err = 0;
1184
1185 k_msgq_get(&evt_msgq, &evt, K_FOREVER);
1186
1187 switch (evt.event) {
1188 case IT82xx2_EVT_SETUP_TOKEN:
1189 err = work_handler_setup(evt.dev, evt.ep);
1190 break;
1191 case IT82xx2_EVT_IN_TOKEN:
1192 err = work_handler_in(evt.dev, evt.ep);
1193 break;
1194 case IT82xx2_EVT_OUT_TOKEN:
1195 err = work_handler_out(evt.dev, evt.ep);
1196 break;
1197 case IT82xx2_EVT_XFER:
1198 break;
1199 default:
1200 LOG_ERR("Unknown event type 0x%x", evt.event);
1201 err = -EINVAL;
1202 break;
1203 }
1204
1205 if (err) {
1206 udc_submit_event(evt.dev, UDC_EVT_ERROR, err);
1207 }
1208
1209 if (evt.ep != USB_CONTROL_EP_OUT && !udc_ep_is_busy(evt.dev, evt.ep)) {
1210 if (work_handler_xfer_next(evt.dev, evt.ep) == 0) {
1211 udc_ep_set_busy(evt.dev, evt.ep, true);
1212 }
1213 }
1214 }
1215 }
1216
it82xx2_check_ep0_stall(const struct device * dev,const uint8_t ep_idx,const uint8_t transtype)1217 static inline bool it82xx2_check_ep0_stall(const struct device *dev, const uint8_t ep_idx,
1218 const uint8_t transtype)
1219 {
1220 const struct usb_it82xx2_config *config = dev->config;
1221 struct usb_it82xx2_regs *const usb_regs = config->base;
1222 struct it82xx2_usb_ep_regs *ep_regs = usb_regs->usb_ep_regs;
1223 struct it82xx2_usb_ep_fifo_regs *ff_regs = usb_regs->fifo_regs;
1224
1225 if (ep_idx != 0) {
1226 return false;
1227 }
1228
1229 /* Check if the stall bit is set */
1230 if (ep_regs[ep_idx].ep_ctrl.fields.send_stall_bit) {
1231 it82xx2_usb_set_ep_ctrl(dev, ep_idx, EP_STALL_SEND, false);
1232 if (transtype == DC_SETUP_TRANS) {
1233 ff_regs[ep_idx].ep_rx_fifo_ctrl = FIFO_FORCE_EMPTY;
1234 }
1235 LOG_ERR("Cleared stall bit");
1236 return true;
1237 }
1238
1239 /* Check if the IN transaction is STALL */
1240 if ((transtype == DC_IN_TRANS) && (ep_regs[ep_idx].ep_status & DC_STALL_SENT)) {
1241 return true;
1242 }
1243
1244 return false;
1245 }
1246
it82xx2_usb_xfer_done(const struct device * dev)1247 static void it82xx2_usb_xfer_done(const struct device *dev)
1248 {
1249 const struct usb_it82xx2_config *config = dev->config;
1250 struct usb_it82xx2_regs *const usb_regs = config->base;
1251 struct it82xx2_usb_ep_regs *ep_regs = usb_regs->usb_ep_regs;
1252 struct epn_ext_ctrl_regs *epn_ext_ctrl =
1253 usb_regs->fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl;
1254
1255 for (uint8_t fifo_idx = 0; fifo_idx < 4; fifo_idx++) {
1256 bool enable_bit, ready_bit;
1257 uint8_t ep, ep_idx, ep_ctrl, transtype;
1258
1259 ep_ctrl = ep_regs[fifo_idx].ep_ctrl.value;
1260 transtype = ep_regs[fifo_idx].ep_transtype_sts & DC_ALL_TRANS;
1261
1262 if (fifo_idx == 0) {
1263 ep_idx = 0;
1264 if (it82xx2_check_ep0_stall(dev, ep_idx, transtype)) {
1265 continue;
1266 }
1267 } else {
1268 ep_idx = (epn_ext_ctrl[fifo_idx].epn_ext_ctrl2 & COMPLETED_TRANS) >> 4;
1269 if (ep_idx == 0) {
1270 continue;
1271 }
1272 }
1273
1274 if (IT8XXX2_IS_EXTEND_ENDPOINT(ep_idx)) {
1275 enable_bit = get_extend_enable_bit(dev, ep_idx);
1276 ready_bit = get_extend_ready_bit(dev, ep_idx);
1277 } else {
1278 enable_bit = (ep_regs[ep_idx].ep_ctrl.fields.enable_bit != 0);
1279 ready_bit = (ep_regs[ep_idx].ep_ctrl.fields.ready_bit != 0);
1280 }
1281
1282 /* The enable bit is set and the ready bit is cleared if the
1283 * transaction is completed.
1284 */
1285 if (!enable_bit || ready_bit) {
1286 continue;
1287 }
1288
1289 if (ep_idx != 0) {
1290 if (it82xx2_fake_token(dev, ep_idx, transtype)) {
1291 continue;
1292 }
1293 }
1294
1295 switch (transtype) {
1296 case DC_SETUP_TRANS:
1297 /* SETUP transaction done */
1298 it82xx2_event_submit(dev, ep_idx, IT82xx2_EVT_SETUP_TOKEN);
1299 break;
1300 case DC_IN_TRANS:
1301 /* IN transaction done */
1302 ep = USB_EP_DIR_IN | ep_idx;
1303 it82xx2_event_submit(dev, ep, IT82xx2_EVT_IN_TOKEN);
1304 break;
1305 case DC_OUTDATA_TRANS:
1306 /* OUT transaction done */
1307 ep = USB_EP_DIR_OUT | ep_idx;
1308 it82xx2_event_submit(dev, ep, IT82xx2_EVT_OUT_TOKEN);
1309 break;
1310 default:
1311 LOG_ERR("Unknown transaction type");
1312 break;
1313 }
1314 }
1315 }
1316
emit_resume_event(const struct device * dev)1317 static inline void emit_resume_event(const struct device *dev)
1318 {
1319 struct it82xx2_data *priv = udc_get_private(dev);
1320
1321 if (udc_is_suspended(dev) && udc_is_enabled(dev)) {
1322 udc_set_suspended(dev, false);
1323 udc_submit_event(dev, UDC_EVT_RESUME, 0);
1324 k_sem_give(&priv->suspended_sem);
1325 }
1326 }
1327
it82xx2_usb_dc_isr(const void * arg)1328 static void it82xx2_usb_dc_isr(const void *arg)
1329 {
1330 const struct device *dev = arg;
1331 const struct usb_it82xx2_config *config = dev->config;
1332 struct usb_it82xx2_regs *const usb_regs = config->base;
1333 struct it82xx2_data *priv = udc_get_private(dev);
1334
1335 uint8_t status = usb_regs->dc_interrupt_status &
1336 usb_regs->dc_interrupt_mask; /* mask non enable int */
1337
1338 /* reset event */
1339 if (status & DC_RESET_EVENT) {
1340 if ((usb_regs->dc_line_status & RX_LINE_STATE_MASK) == RX_LINE_RESET) {
1341 it82xx2_dc_reset(dev);
1342 usb_regs->dc_interrupt_status = DC_RESET_EVENT;
1343
1344 udc_submit_event(dev, UDC_EVT_RESET, 0);
1345 return;
1346 }
1347 usb_regs->dc_interrupt_status = DC_RESET_EVENT;
1348 }
1349
1350 /* sof received */
1351 if (status & DC_SOF_RECEIVED) {
1352 if (!USB_DEVICE_CONFIG_SOF_NOTIFICATIONS) {
1353 it82xx2_enable_sof_int(dev, false);
1354 } else {
1355 usb_regs->dc_interrupt_status = DC_SOF_RECEIVED;
1356 udc_submit_event(dev, UDC_EVT_SOF, 0);
1357 }
1358 it82xx2_enable_resume_int(dev, false);
1359 emit_resume_event(dev);
1360 k_work_cancel_delayable(&priv->suspended_work);
1361 k_work_reschedule(&priv->suspended_work, K_MSEC(5));
1362 }
1363
1364 /* resume event */
1365 if (status & DC_RESUME_EVENT) {
1366 it82xx2_enable_resume_int(dev, false);
1367 emit_resume_event(dev);
1368 }
1369
1370 /* transaction done */
1371 if (status & DC_TRANS_DONE) {
1372 /* clear interrupt before new transaction */
1373 usb_regs->dc_interrupt_status = DC_TRANS_DONE;
1374 it82xx2_usb_xfer_done(dev);
1375 return;
1376 }
1377 }
1378
suspended_handler(struct k_work * item)1379 static void suspended_handler(struct k_work *item)
1380 {
1381 struct k_work_delayable *dwork = k_work_delayable_from_work(item);
1382 struct it82xx2_data *priv = CONTAINER_OF(dwork, struct it82xx2_data, suspended_work);
1383 const struct device *dev = priv->dev;
1384 const struct usb_it82xx2_config *config = dev->config;
1385 struct usb_it82xx2_regs *const usb_regs = config->base;
1386 unsigned int key;
1387
1388 if (usb_regs->dc_interrupt_status & DC_SOF_RECEIVED) {
1389 usb_regs->dc_interrupt_status = DC_SOF_RECEIVED;
1390 k_work_reschedule(&priv->suspended_work, K_MSEC(5));
1391 return;
1392 }
1393
1394 key = irq_lock();
1395 if (!udc_is_suspended(dev) && udc_is_enabled(dev)) {
1396 udc_set_suspended(dev, true);
1397 udc_submit_event(dev, UDC_EVT_SUSPEND, 0);
1398 it82xx2_enable_wu_irq(dev, true);
1399 it82xx2_enable_standby_state(true);
1400
1401 k_sem_reset(&priv->suspended_sem);
1402 }
1403
1404 it82xx2_enable_resume_int(dev, true);
1405
1406 if (!USB_DEVICE_CONFIG_SOF_NOTIFICATIONS) {
1407 it82xx2_enable_sof_int(dev, true);
1408 }
1409
1410 irq_unlock(key);
1411 }
1412
it82xx2_enable(const struct device * dev)1413 static int it82xx2_enable(const struct device *dev)
1414 {
1415 const struct usb_it82xx2_config *config = dev->config;
1416 struct usb_it82xx2_regs *const usb_regs = config->base;
1417 struct it82xx2_data *priv = udc_get_private(dev);
1418
1419 k_sem_init(&priv->suspended_sem, 0, 1);
1420 k_work_init_delayable(&priv->suspended_work, suspended_handler);
1421
1422 atomic_clear_bit(&priv->out_fifo_state, IT82xx2_STATE_OUT_SHARED_FIFO_BUSY);
1423
1424 /* Initialize FIFO semaphore */
1425 k_sem_init(&priv->fifo_sem[0], 1, 1);
1426 k_sem_init(&priv->fifo_sem[1], 1, 1);
1427 k_sem_init(&priv->fifo_sem[2], 1, 1);
1428
1429 usb_regs->dc_control = DC_GLOBAL_ENABLE | DC_FULL_SPEED_LINE_POLARITY |
1430 DC_FULL_SPEED_LINE_RATE | DC_CONNECT_TO_HOST;
1431
1432 /* Enable USB D+ and USB interrupts */
1433 it82xx2_enable_wu_irq(dev, true);
1434 irq_enable(config->usb_irq);
1435
1436 return 0;
1437 }
1438
it82xx2_disable(const struct device * dev)1439 static int it82xx2_disable(const struct device *dev)
1440 {
1441 const struct usb_it82xx2_config *config = dev->config;
1442 struct usb_it82xx2_regs *const usb_regs = config->base;
1443
1444 irq_disable(config->usb_irq);
1445
1446 /* stop pull-up D+ D-*/
1447 usb_regs->dc_control &= ~DC_CONNECT_TO_HOST;
1448
1449 return 0;
1450 }
1451
it82xx2_init(const struct device * dev)1452 static int it82xx2_init(const struct device *dev)
1453 {
1454 const struct usb_it82xx2_config *config = dev->config;
1455 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
1456 int ret;
1457
1458 /*
1459 * Disable USB debug path , prevent CPU enter
1460 * JTAG mode and then reset by USB command.
1461 */
1462 gctrl_regs->GCTRL_MCCR &= ~(IT8XXX2_GCTRL_MCCR_USB_EN);
1463 gctrl_regs->gctrl_pmer2 |= IT8XXX2_GCTRL_PMER2_USB_PAD_EN;
1464
1465 it82xx2_usb_dc_ip_init(dev);
1466
1467 ret = udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT, USB_EP_TYPE_CONTROL,
1468 config->ep_cfg_out[0].caps.mps, 0);
1469 if (ret) {
1470 LOG_ERR("Failed to enable ep 0x%02x", USB_CONTROL_EP_OUT);
1471 return ret;
1472 }
1473
1474 ret = udc_ep_enable_internal(dev, USB_CONTROL_EP_IN, USB_EP_TYPE_CONTROL,
1475 config->ep_cfg_in[0].caps.mps, 0);
1476 if (ret) {
1477 LOG_ERR("Failed to enable ep 0x%02x", USB_CONTROL_EP_IN);
1478 return ret;
1479 }
1480 return 0;
1481 }
1482
it82xx2_shutdown(const struct device * dev)1483 static int it82xx2_shutdown(const struct device *dev)
1484 {
1485 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_OUT)) {
1486 LOG_ERR("Failed to disable control endpoint");
1487 return -EIO;
1488 }
1489
1490 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_IN)) {
1491 LOG_ERR("Failed to disable control endpoint");
1492 return -EIO;
1493 }
1494
1495 return 0;
1496 }
1497
it82xx2_lock(const struct device * dev)1498 static int it82xx2_lock(const struct device *dev)
1499 {
1500 return udc_lock_internal(dev, K_FOREVER);
1501 }
1502
it82xx2_unlock(const struct device * dev)1503 static int it82xx2_unlock(const struct device *dev)
1504 {
1505 return udc_unlock_internal(dev);
1506 }
1507
1508 static const struct udc_api it82xx2_api = {
1509 .ep_enqueue = it82xx2_ep_enqueue,
1510 .ep_dequeue = it82xx2_ep_dequeue,
1511 .ep_set_halt = it82xx2_ep_set_halt,
1512 .ep_clear_halt = it82xx2_ep_clear_halt,
1513 .ep_try_config = NULL,
1514 .ep_enable = it82xx2_ep_enable,
1515 .ep_disable = it82xx2_ep_disable,
1516 .host_wakeup = it82xx2_host_wakeup,
1517 .set_address = it82xx2_set_address,
1518 .enable = it82xx2_enable,
1519 .disable = it82xx2_disable,
1520 .init = it82xx2_init,
1521 .shutdown = it82xx2_shutdown,
1522 .lock = it82xx2_lock,
1523 .unlock = it82xx2_unlock,
1524 };
1525
it82xx2_usb_driver_preinit(const struct device * dev)1526 static int it82xx2_usb_driver_preinit(const struct device *dev)
1527 {
1528 const struct usb_it82xx2_config *config = dev->config;
1529 struct udc_data *data = dev->data;
1530 struct it82xx2_data *priv = udc_get_private(dev);
1531 int err;
1532
1533 k_mutex_init(&data->mutex);
1534 k_fifo_init(&priv->fifo);
1535
1536 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1537 if (err < 0) {
1538 LOG_ERR("Failed to configure usb pins");
1539 return err;
1540 }
1541
1542 for (int i = 0; i < MAX_NUM_ENDPOINTS; i++) {
1543 config->ep_cfg_out[i].caps.out = 1;
1544 if (i == 0) {
1545 config->ep_cfg_out[i].caps.control = 1;
1546 config->ep_cfg_out[i].caps.mps = USB_CONTROL_EP_MPS;
1547 } else if ((i % 3) == 2) {
1548 config->ep_cfg_out[i].caps.bulk = 1;
1549 config->ep_cfg_out[i].caps.interrupt = 1;
1550 config->ep_cfg_out[i].caps.iso = 1;
1551 config->ep_cfg_out[i].caps.mps = 64;
1552 }
1553
1554 config->ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
1555 err = udc_register_ep(dev, &config->ep_cfg_out[i]);
1556 if (err != 0) {
1557 LOG_ERR("Failed to register endpoint");
1558 return err;
1559 }
1560 }
1561
1562 for (int i = 0; i < MAX_NUM_ENDPOINTS; i++) {
1563 config->ep_cfg_in[i].caps.in = 1;
1564 if (i == 0) {
1565 config->ep_cfg_in[i].caps.control = 1;
1566 config->ep_cfg_in[i].caps.mps = USB_CONTROL_EP_MPS;
1567 } else if ((i % 3) != 2) {
1568 config->ep_cfg_in[i].caps.bulk = 1;
1569 config->ep_cfg_in[i].caps.interrupt = 1;
1570 config->ep_cfg_in[i].caps.iso = 1;
1571 config->ep_cfg_in[i].caps.mps = 64;
1572 }
1573
1574 config->ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
1575 err = udc_register_ep(dev, &config->ep_cfg_in[i]);
1576 if (err != 0) {
1577 LOG_ERR("Failed to register endpoint");
1578 return err;
1579 }
1580 }
1581
1582 data->caps.rwup = true;
1583 data->caps.mps0 = UDC_MPS0_64;
1584
1585 priv->dev = dev;
1586
1587 config->make_thread(dev);
1588
1589 /* Initializing WU (USB D+) */
1590 it8xxx2_usb_dc_wuc_init(dev);
1591
1592 /* Connect USB interrupt */
1593 irq_connect_dynamic(config->usb_irq, 0, it82xx2_usb_dc_isr, dev, 0);
1594
1595 return 0;
1596 }
1597
1598 #define IT82xx2_USB_DEVICE_DEFINE(n) \
1599 K_KERNEL_STACK_DEFINE(udc_it82xx2_stack_##n, CONFIG_UDC_IT82xx2_STACK_SIZE); \
1600 \
1601 static void udc_it82xx2_thread_##n(void *dev, void *arg1, void *arg2) \
1602 { \
1603 ARG_UNUSED(arg1); \
1604 ARG_UNUSED(arg2); \
1605 xfer_work_handler(dev); \
1606 } \
1607 \
1608 static void udc_it82xx2_make_thread_##n(const struct device *dev) \
1609 { \
1610 struct it82xx2_data *priv = udc_get_private(dev); \
1611 \
1612 k_thread_create(&priv->thread_data, udc_it82xx2_stack_##n, \
1613 K_THREAD_STACK_SIZEOF(udc_it82xx2_stack_##n), \
1614 udc_it82xx2_thread_##n, (void *)dev, NULL, NULL, K_PRIO_COOP(8), \
1615 0, K_NO_WAIT); \
1616 k_thread_name_set(&priv->thread_data, dev->name); \
1617 } \
1618 \
1619 PINCTRL_DT_INST_DEFINE(n); \
1620 \
1621 static struct udc_ep_config ep_cfg_out[MAX_NUM_ENDPOINTS]; \
1622 static struct udc_ep_config ep_cfg_in[MAX_NUM_ENDPOINTS]; \
1623 \
1624 static struct usb_it82xx2_config udc_cfg_##n = { \
1625 .base = (struct usb_it82xx2_regs *)DT_INST_REG_ADDR(n), \
1626 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
1627 .wuc = {.dev = IT8XXX2_DEV_WUC(0, n), .mask = IT8XXX2_DEV_WUC_MASK(0, n)}, \
1628 .usb_irq = DT_INST_IRQ_BY_IDX(n, 0, irq), \
1629 .wu_irq = DT_INST_IRQ_BY_IDX(n, 1, irq), \
1630 .ep_cfg_in = ep_cfg_out, \
1631 .ep_cfg_out = ep_cfg_in, \
1632 .make_thread = udc_it82xx2_make_thread_##n, \
1633 }; \
1634 \
1635 static struct it82xx2_data priv_data_##n = {}; \
1636 \
1637 static struct udc_data udc_data_##n = { \
1638 .mutex = Z_MUTEX_INITIALIZER(udc_data_##n.mutex), \
1639 .priv = &priv_data_##n, \
1640 }; \
1641 \
1642 DEVICE_DT_INST_DEFINE(n, it82xx2_usb_driver_preinit, NULL, &udc_data_##n, &udc_cfg_##n, \
1643 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &it82xx2_api);
1644
1645 DT_INST_FOREACH_STATUS_OKAY(IT82xx2_USB_DEVICE_DEFINE)
1646
