1 /* Copyright (C) 2023 BeagleBoard.org Foundation
2 * Copyright (C) 2023 S Prashanth
3 * Copyright (c) 2024 Texas Instruments Incorporated
4 * Andrew Davis <afd@ti.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/timer/system_timer.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/sys_clock.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/spinlock.h>
15
16 #include <zephyr/drivers/timer/ti_dmtimer.h>
17
18 #define DT_DRV_COMPAT ti_am654_timer
19
20 #define TIMER_BASE_ADDR DT_INST_REG_ADDR(0)
21
22 #define TIMER_IRQ_NUM DT_INST_IRQN(0)
23 #define TIMER_IRQ_PRIO DT_INST_IRQ(0, priority)
24 #define TIMER_IRQ_FLAGS DT_INST_IRQ(0, flags)
25
26 #define CYC_PER_TICK ((uint32_t)(sys_clock_hw_cycles_per_sec() \
27 / CONFIG_SYS_CLOCK_TICKS_PER_SEC))
28
29 #define MAX_TICKS ((k_ticks_t)(UINT32_MAX / CYC_PER_TICK) - 1)
30
31 static struct k_spinlock lock;
32
33 static uint32_t last_cycle;
34
35 #define TI_DM_TIMER_READ(reg) sys_read32(TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg)
36
37 #define TI_DM_TIMER_MASK(reg) TI_DM_TIMER_ ## reg ## _MASK
38 #define TI_DM_TIMER_SHIFT(reg) TI_DM_TIMER_ ## reg ## _SHIFT
39 #define TI_DM_TIMER_WRITE(data, reg, bits) \
40 ti_dm_timer_write_masks(data, \
41 TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg, \
42 TI_DM_TIMER_MASK(reg ## _ ## bits), \
43 TI_DM_TIMER_SHIFT(reg ## _ ## bits))
44
ti_dm_timer_write_masks(uint32_t data,uint32_t reg,uint32_t mask,uint32_t shift)45 static void ti_dm_timer_write_masks(uint32_t data, uint32_t reg, uint32_t mask, uint32_t shift)
46 {
47 uint32_t reg_val;
48
49 reg_val = sys_read32(reg);
50 reg_val = (reg_val & ~(mask)) | (data << shift);
51 sys_write32(reg_val, reg);
52 }
53
ti_dmtimer_isr(void * data)54 static void ti_dmtimer_isr(void *data)
55 {
56 /* If no pending event */
57 if (!TI_DM_TIMER_READ(IRQSTATUS)) {
58 return;
59 }
60
61 k_spinlock_key_t key = k_spin_lock(&lock);
62
63 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
64 uint32_t delta_cycles = curr_cycle - last_cycle;
65 uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
66
67 last_cycle = curr_cycle;
68
69 /* ACK match interrupt */
70 TI_DM_TIMER_WRITE(1, IRQSTATUS, MAT_IT_FLAG);
71
72 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
73 /* Setup next match time */
74 uint64_t next_cycle = curr_cycle + CYC_PER_TICK;
75
76 TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
77 }
78
79 k_spin_unlock(&lock, key);
80
81 sys_clock_announce(delta_ticks);
82 }
83
sys_clock_set_timeout(int32_t ticks,bool idle)84 void sys_clock_set_timeout(int32_t ticks, bool idle)
85 {
86 ARG_UNUSED(idle);
87 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
88 /* Not supported on tickful kernels */
89 return;
90 }
91
92 ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
93 ticks = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
94
95 k_spinlock_key_t key = k_spin_lock(&lock);
96
97 /* Setup next match time */
98 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
99 uint32_t next_cycle = curr_cycle + (ticks * CYC_PER_TICK);
100
101 TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
102
103 k_spin_unlock(&lock, key);
104 }
105
sys_clock_cycle_get_32(void)106 uint32_t sys_clock_cycle_get_32(void)
107 {
108 k_spinlock_key_t key = k_spin_lock(&lock);
109
110 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
111
112 k_spin_unlock(&lock, key);
113
114 return curr_cycle;
115 }
116
sys_clock_elapsed(void)117 unsigned int sys_clock_elapsed(void)
118 {
119 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
120 /* Always return 0 for tickful kernel system */
121 return 0;
122 }
123
124 k_spinlock_key_t key = k_spin_lock(&lock);
125
126 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
127 uint32_t delta_cycles = curr_cycle - last_cycle;
128 uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
129
130 k_spin_unlock(&lock, key);
131
132 return delta_ticks;
133 }
134
sys_clock_driver_init(void)135 static int sys_clock_driver_init(void)
136 {
137 last_cycle = 0;
138
139 IRQ_CONNECT(TIMER_IRQ_NUM, TIMER_IRQ_PRIO, ti_dmtimer_isr, NULL, TIMER_IRQ_FLAGS);
140
141 /* Disable prescalar */
142 TI_DM_TIMER_WRITE(0, TCLR, PRE);
143
144 /* Select autoreload mode */
145 TI_DM_TIMER_WRITE(1, TCLR, AR);
146
147 /* Enable match interrupt */
148 TI_DM_TIMER_WRITE(1, IRQENABLE_SET, MAT_EN_FLAG);
149
150 /* Load timer counter value */
151 TI_DM_TIMER_WRITE(0, TCRR, TIMER_COUNTER);
152
153 /* Load timer load value */
154 TI_DM_TIMER_WRITE(0, TLDR, LOAD_VALUE);
155
156 /* Load timer compare value */
157 TI_DM_TIMER_WRITE(CYC_PER_TICK, TMAR, COMPARE_VALUE);
158
159 /* Enable compare mode */
160 TI_DM_TIMER_WRITE(1, TCLR, CE);
161
162 /* Start the timer */
163 TI_DM_TIMER_WRITE(1, TCLR, ST);
164
165 irq_enable(TIMER_IRQ_NUM);
166
167 return 0;
168 }
169
170 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
171 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
172
