1# Copyright (c) 2014-2015 Wind River Systems, Inc.
2# Copyright (c) 2016 Cadence Design Systems, Inc.
3# Copyright (c) 2019 Intel Corp.
4# SPDX-License-Identifier: Apache-2.0
5
6config XTENSA_TIMER
7	bool "Xtensa timer support"
8	depends on XTENSA
9	default y
10	select TICKLESS_CAPABLE
11	help
12	  Enables a system timer driver for Xtensa based on the CCOUNT
13	  and CCOMPARE special registers.
14
15config XTENSA_TIMER_ID
16	int "System timer CCOMPAREn register index"
17	default 0
18	depends on XTENSA_TIMER
19	help
20	  Index of the CCOMPARE register (and associated interrupt)
21	  used for the system timer.  Xtensa CPUs have hard-configured
22	  interrupt priorities associated with each timer, and some of
23	  them can be unmaskable (and thus not usable by OS code that
24	  need synchronization, like the timer subsystem!).  In
25	  general timer zero is guaranteed to be present and usable.
26