1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_ 7 #define ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_ 8 9 #include <zephyr/drivers/spi.h> 10 #include <zephyr/drivers/spi/rtio.h> 11 #include <zephyr/logging/log.h> 12 13 #define LOG_LEVEL CONFIG_SPI_LOG_LEVEL 14 LOG_MODULE_REGISTER(spi_nxp_s32); 15 16 #include "spi_context.h" 17 18 #include <Spi_Ip.h> 19 20 #define SPI_NXP_S32_NUM_PRESCALER 4U 21 #define SPI_NXP_S32_NUM_SCALER 16U 22 23 /* Modified SPI transfer format is not supported, 24 * the maximum baudrate is 25Mhz. 25 */ 26 #define SPI_NXP_S32_MIN_FREQ 100000U 27 #define SPI_NXP_S32_MAX_FREQ 25000000U 28 29 #define SPI_NXP_S32_BYTE_PER_FRAME(frame_size) \ 30 (frame_size <= 8U) ? 1U : ((frame_size <= 16U) ? 2U : 4U) 31 32 #define SPI_NXP_S32_MAX_BYTES_PER_PACKAGE(bytes_per_frame) \ 33 ((UINT16_MAX / bytes_per_frame) * bytes_per_frame) 34 35 struct spi_nxp_s32_baudrate_param { 36 uint8_t scaler; 37 uint8_t prescaler; 38 uint32_t frequency; 39 }; 40 41 struct spi_nxp_s32_data { 42 uint8_t bytes_per_frame; 43 uint32_t transfer_len; 44 struct spi_context ctx; 45 46 Spi_Ip_ExternalDeviceType transfer_cfg; 47 Spi_Ip_DeviceParamsType transfer_params; 48 }; 49 50 struct spi_nxp_s32_config { 51 uint8_t num_cs; 52 const struct device *clock_dev; 53 clock_control_subsys_t clock_subsys; 54 uint32_t sck_cs_delay; 55 uint32_t cs_sck_delay; 56 uint32_t cs_cs_delay; 57 58 Spi_Ip_ConfigType *spi_hw_cfg; 59 const struct pinctrl_dev_config *pincfg; 60 61 #ifdef CONFIG_NXP_S32_SPI_INTERRUPT 62 Spi_Ip_CallbackType cb; 63 void (*irq_config_func)(const struct device *dev); 64 #endif /* CONFIG_NXP_S32_SPI_INTERRUPT */ 65 }; 66 67 #endif /* ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_ */ 68
