1 /*
2 * Copyright (c) 2018 Linaro Limited
3 * Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved.
4 * Copyright (c) 2023 Antmicro <www.antmicro.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define DT_DRV_COMPAT arm_pl011
10 #define SBSA_COMPAT arm_sbsa_uart
11
12 #include <string.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/arch/cpu.h>
15 #include <zephyr/init.h>
16 #include <zephyr/device.h>
17 #include <zephyr/drivers/uart.h>
18 #include <zephyr/sys/device_mmio.h>
19 #include <zephyr/sys/barrier.h>
20 #include <zephyr/irq.h>
21 #if defined(CONFIG_PINCTRL)
22 #include <zephyr/drivers/pinctrl.h>
23 #endif
24 #if defined(CONFIG_RESET)
25 #include <zephyr/drivers/reset.h>
26 #endif
27 #if defined(CONFIG_CLOCK_CONTROL)
28 #include <zephyr/drivers/clock_control.h>
29 #endif
30
31 #ifdef CONFIG_CPU_CORTEX_M
32 #include <cmsis_compiler.h>
33 #endif
34
35 #include "uart_pl011_registers.h"
36
37 #if defined(CONFIG_SOC_FAMILY_AMBIQ)
38 #include "uart_pl011_ambiq.h"
39 #endif
40
41 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
42 #define PM_INST_GET(n) PM_DEVICE_DT_INST_GET(n)
43 #else
44 #define PM_INST_GET(n) NULL
45 #endif
46
47 #include "uart_pl011_raspberrypi_pico.h"
48
49 struct pl011_config {
50 DEVICE_MMIO_ROM;
51 #if defined(CONFIG_PINCTRL)
52 const struct pinctrl_dev_config *pincfg;
53 #endif
54 #if defined(CONFIG_RESET)
55 const struct reset_dt_spec reset;
56 #endif
57 #if defined(CONFIG_CLOCK_CONTROL)
58 const struct device *clock_dev;
59 clock_control_subsys_t clock_id;
60 #endif
61 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
62 uart_irq_config_func_t irq_config_func;
63 #endif
64 int (*clk_enable_func)(const struct device *dev, uint32_t clk);
65 int (*pwr_on_func)(void);
66 };
67
68 /* Device data structure */
69 struct pl011_data {
70 DEVICE_MMIO_RAM;
71 struct uart_config uart_cfg;
72 bool sbsa; /* SBSA mode */
73 uint32_t clk_freq;
74 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
75 volatile bool sw_call_txdrdy;
76 uart_irq_callback_user_data_t irq_cb;
77 void *irq_cb_data;
78 #endif
79 };
80
pl011_enable(const struct device * dev)81 static void pl011_enable(const struct device *dev)
82 {
83 get_uart(dev)->cr |= PL011_CR_UARTEN;
84 }
85
pl011_disable(const struct device * dev)86 static void pl011_disable(const struct device *dev)
87 {
88 get_uart(dev)->cr &= ~PL011_CR_UARTEN;
89 }
90
pl011_enable_fifo(const struct device * dev)91 static void pl011_enable_fifo(const struct device *dev)
92 {
93 get_uart(dev)->lcr_h |= PL011_LCRH_FEN;
94 }
95
pl011_disable_fifo(const struct device * dev)96 static void pl011_disable_fifo(const struct device *dev)
97 {
98 get_uart(dev)->lcr_h &= ~PL011_LCRH_FEN;
99 }
100
pl011_set_flow_control(const struct device * dev,bool rts,bool cts)101 static void pl011_set_flow_control(const struct device *dev, bool rts, bool cts)
102 {
103 if (rts) {
104 get_uart(dev)->cr |= PL011_CR_RTSEn;
105 } else {
106 get_uart(dev)->cr &= ~PL011_CR_RTSEn;
107 }
108 if (cts) {
109 get_uart(dev)->cr |= PL011_CR_CTSEn;
110 } else {
111 get_uart(dev)->cr &= ~PL011_CR_CTSEn;
112 }
113 }
114
pl011_set_baudrate(const struct device * dev,uint32_t clk,uint32_t baudrate)115 static int pl011_set_baudrate(const struct device *dev,
116 uint32_t clk, uint32_t baudrate)
117 {
118 /* Avoiding float calculations, bauddiv is left shifted by 6 */
119 uint64_t bauddiv = (((uint64_t)clk) << PL011_FBRD_WIDTH)
120 / (baudrate * 16U);
121
122 /* Valid bauddiv value
123 * uart_clk (min) >= 16 x baud_rate (max)
124 * uart_clk (max) <= 16 x 65535 x baud_rate (min)
125 */
126 if ((bauddiv < (1u << PL011_FBRD_WIDTH))
127 || (bauddiv > (65535u << PL011_FBRD_WIDTH))) {
128 return -EINVAL;
129 }
130
131 get_uart(dev)->ibrd = bauddiv >> PL011_FBRD_WIDTH;
132 get_uart(dev)->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
133
134 barrier_dmem_fence_full();
135
136 /* In order to internally update the contents of ibrd or fbrd, a
137 * lcr_h write must always be performed at the end
138 * ARM DDI 0183F, Pg 3-13
139 */
140 get_uart(dev)->lcr_h = get_uart(dev)->lcr_h;
141
142 return 0;
143 }
144
pl011_is_readable(const struct device * dev)145 static bool pl011_is_readable(const struct device *dev)
146 {
147 struct pl011_data *data = dev->data;
148
149 if (!data->sbsa &&
150 (!(get_uart(dev)->cr & PL011_CR_UARTEN) || !(get_uart(dev)->cr & PL011_CR_RXE))) {
151 return false;
152 }
153
154 return (get_uart(dev)->fr & PL011_FR_RXFE) == 0U;
155 }
156
pl011_poll_in(const struct device * dev,unsigned char * c)157 static int pl011_poll_in(const struct device *dev, unsigned char *c)
158 {
159 if (!pl011_is_readable(dev)) {
160 return -1;
161 }
162
163 /* got a character */
164 *c = (unsigned char)get_uart(dev)->dr;
165
166 return get_uart(dev)->rsr & PL011_RSR_ERROR_MASK;
167 }
168
pl011_poll_out(const struct device * dev,unsigned char c)169 static void pl011_poll_out(const struct device *dev,
170 unsigned char c)
171 {
172 /* Wait for space in FIFO */
173 while (get_uart(dev)->fr & PL011_FR_TXFF) {
174 ; /* Wait */
175 }
176
177 /* Send a character */
178 get_uart(dev)->dr = (uint32_t)c;
179 }
180
pl011_err_check(const struct device * dev)181 static int pl011_err_check(const struct device *dev)
182 {
183 int errors = 0;
184
185 if (get_uart(dev)->rsr & PL011_RSR_ECR_OE) {
186 errors |= UART_ERROR_OVERRUN;
187 }
188
189 if (get_uart(dev)->rsr & PL011_RSR_ECR_BE) {
190 errors |= UART_BREAK;
191 }
192
193 if (get_uart(dev)->rsr & PL011_RSR_ECR_PE) {
194 errors |= UART_ERROR_PARITY;
195 }
196
197 if (get_uart(dev)->rsr & PL011_RSR_ECR_FE) {
198 errors |= UART_ERROR_FRAMING;
199 }
200
201 return errors;
202 }
203
pl011_runtime_configure_internal(const struct device * dev,const struct uart_config * cfg,bool disable)204 static int pl011_runtime_configure_internal(const struct device *dev,
205 const struct uart_config *cfg,
206 bool disable)
207 {
208 struct pl011_data *data = dev->data;
209 uint32_t lcrh;
210 int ret = -ENOTSUP;
211
212 if (data->sbsa) {
213 goto out;
214 }
215
216 if (disable) {
217 pl011_disable(dev);
218 pl011_disable_fifo(dev);
219 }
220
221 lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK | PL011_LCRH_STP2);
222
223 switch (cfg->parity) {
224 case UART_CFG_PARITY_NONE:
225 lcrh &= ~(BIT(1) | BIT(2));
226 break;
227 case UART_CFG_PARITY_ODD:
228 lcrh |= PL011_LCRH_PARITY_ODD;
229 break;
230 case UART_CFG_PARITY_EVEN:
231 lcrh |= PL011_LCRH_PARTIY_EVEN;
232 break;
233 default:
234 goto enable;
235 }
236
237 switch (cfg->stop_bits) {
238 case UART_CFG_STOP_BITS_1:
239 lcrh &= ~(PL011_LCRH_STP2);
240 break;
241 case UART_CFG_STOP_BITS_2:
242 lcrh |= PL011_LCRH_STP2;
243 break;
244 default:
245 goto enable;
246 }
247
248 switch (cfg->data_bits) {
249 case UART_CFG_DATA_BITS_5:
250 lcrh |= PL011_LCRH_WLEN_SIZE(5) << PL011_LCRH_WLEN_SHIFT;
251 break;
252 case UART_CFG_DATA_BITS_6:
253 lcrh |= PL011_LCRH_WLEN_SIZE(6) << PL011_LCRH_WLEN_SHIFT;
254 break;
255 case UART_CFG_DATA_BITS_7:
256 lcrh |= PL011_LCRH_WLEN_SIZE(7) << PL011_LCRH_WLEN_SHIFT;
257 break;
258 case UART_CFG_DATA_BITS_8:
259 lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
260 break;
261 default:
262 goto enable;
263 }
264
265 switch (cfg->flow_ctrl) {
266 case UART_CFG_FLOW_CTRL_NONE:
267 pl011_set_flow_control(dev, false, false);
268 break;
269 case UART_CFG_FLOW_CTRL_RTS_CTS:
270 pl011_set_flow_control(dev, true, true);
271 break;
272 default:
273 goto enable;
274 }
275
276 /* Set baud rate */
277 ret = pl011_set_baudrate(dev, data->clk_freq, cfg->baudrate);
278 if (ret != 0) {
279 goto enable;
280 }
281
282 /* Update settings */
283 get_uart(dev)->lcr_h = lcrh;
284
285 memcpy(&data->uart_cfg, cfg, sizeof(data->uart_cfg));
286
287 enable:
288 if (disable) {
289 pl011_enable_fifo(dev);
290 pl011_enable(dev);
291 }
292
293 out:
294 return ret;
295 }
296
297 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
298
pl011_runtime_configure(const struct device * dev,const struct uart_config * cfg)299 static int pl011_runtime_configure(const struct device *dev,
300 const struct uart_config *cfg)
301 {
302 return pl011_runtime_configure_internal(dev, cfg, true);
303 }
304
pl011_runtime_config_get(const struct device * dev,struct uart_config * cfg)305 static int pl011_runtime_config_get(const struct device *dev,
306 struct uart_config *cfg)
307 {
308 struct pl011_data *data = dev->data;
309
310 *cfg = data->uart_cfg;
311 return 0;
312 }
313
314 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
315
316 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
pl011_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)317 static int pl011_fifo_fill(const struct device *dev,
318 const uint8_t *tx_data, int len)
319 {
320 int num_tx = 0U;
321
322 while (!(get_uart(dev)->fr & PL011_FR_TXFF) && (len - num_tx > 0)) {
323 get_uart(dev)->dr = tx_data[num_tx++];
324 }
325 return num_tx;
326 }
327
pl011_fifo_read(const struct device * dev,uint8_t * rx_data,const int len)328 static int pl011_fifo_read(const struct device *dev,
329 uint8_t *rx_data, const int len)
330 {
331 int num_rx = 0U;
332
333 while ((len - num_rx > 0) && !(get_uart(dev)->fr & PL011_FR_RXFE)) {
334 rx_data[num_rx++] = get_uart(dev)->dr;
335 }
336
337 return num_rx;
338 }
339
pl011_irq_tx_enable(const struct device * dev)340 static void pl011_irq_tx_enable(const struct device *dev)
341 {
342 struct pl011_data *data = dev->data;
343
344 get_uart(dev)->imsc |= PL011_IMSC_TXIM;
345 if (data->sw_call_txdrdy) {
346 /* Verify if the callback has been registered */
347 if (data->irq_cb) {
348 /*
349 * Due to HW limitation, the first TX interrupt should
350 * be triggered by the software.
351 *
352 * PL011 TX interrupt is based on a transition through
353 * a level, rather than on the level itself[1]. So that,
354 * enable TX interrupt can not trigger TX interrupt if
355 * no data was filled to TX FIFO at the beginning.
356 *
357 * [1]: PrimeCell UART (PL011) Technical Reference Manual
358 * functional-overview/interrupts
359 */
360 data->irq_cb(dev, data->irq_cb_data);
361 }
362 data->sw_call_txdrdy = false;
363 }
364 }
365
pl011_irq_tx_disable(const struct device * dev)366 static void pl011_irq_tx_disable(const struct device *dev)
367 {
368 get_uart(dev)->imsc &= ~PL011_IMSC_TXIM;
369 }
370
pl011_irq_tx_complete(const struct device * dev)371 static int pl011_irq_tx_complete(const struct device *dev)
372 {
373 /* Check for UART is busy transmitting data. */
374 return ((get_uart(dev)->fr & PL011_FR_BUSY) == 0);
375 }
376
pl011_irq_tx_ready(const struct device * dev)377 static int pl011_irq_tx_ready(const struct device *dev)
378 {
379 struct pl011_data *data = dev->data;
380
381 if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_TXE)) {
382 return false;
383 }
384
385 return ((get_uart(dev)->imsc & PL011_IMSC_TXIM) &&
386 /* Check for TX interrupt status is set or TX FIFO is empty. */
387 (get_uart(dev)->ris & PL011_RIS_TXRIS || get_uart(dev)->fr & PL011_FR_TXFE));
388 }
389
pl011_irq_rx_enable(const struct device * dev)390 static void pl011_irq_rx_enable(const struct device *dev)
391 {
392 get_uart(dev)->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
393 }
394
pl011_irq_rx_disable(const struct device * dev)395 static void pl011_irq_rx_disable(const struct device *dev)
396 {
397 get_uart(dev)->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
398 }
399
pl011_irq_rx_ready(const struct device * dev)400 static int pl011_irq_rx_ready(const struct device *dev)
401 {
402 struct pl011_data *data = dev->data;
403
404 if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_RXE)) {
405 return false;
406 }
407
408 return ((get_uart(dev)->imsc & PL011_IMSC_RXIM) &&
409 (!(get_uart(dev)->fr & PL011_FR_RXFE)));
410 }
411
pl011_irq_err_enable(const struct device * dev)412 static void pl011_irq_err_enable(const struct device *dev)
413 {
414 /* enable framing, parity, break, and overrun */
415 get_uart(dev)->imsc |= PL011_IMSC_ERROR_MASK;
416 }
417
pl011_irq_err_disable(const struct device * dev)418 static void pl011_irq_err_disable(const struct device *dev)
419 {
420 get_uart(dev)->imsc &= ~PL011_IMSC_ERROR_MASK;
421 }
422
pl011_irq_is_pending(const struct device * dev)423 static int pl011_irq_is_pending(const struct device *dev)
424 {
425 return pl011_irq_rx_ready(dev) || pl011_irq_tx_ready(dev);
426 }
427
pl011_irq_update(const struct device * dev)428 static int pl011_irq_update(const struct device *dev)
429 {
430 return 1;
431 }
432
pl011_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)433 static void pl011_irq_callback_set(const struct device *dev,
434 uart_irq_callback_user_data_t cb,
435 void *cb_data)
436 {
437 struct pl011_data *data = dev->data;
438
439 data->irq_cb = cb;
440 data->irq_cb_data = cb_data;
441 }
442 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
443
444 static DEVICE_API(uart, pl011_driver_api) = {
445 .poll_in = pl011_poll_in,
446 .poll_out = pl011_poll_out,
447 .err_check = pl011_err_check,
448 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
449 .configure = pl011_runtime_configure,
450 .config_get = pl011_runtime_config_get,
451 #endif
452 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
453 .fifo_fill = pl011_fifo_fill,
454 .fifo_read = pl011_fifo_read,
455 .irq_tx_enable = pl011_irq_tx_enable,
456 .irq_tx_disable = pl011_irq_tx_disable,
457 .irq_tx_ready = pl011_irq_tx_ready,
458 .irq_rx_enable = pl011_irq_rx_enable,
459 .irq_rx_disable = pl011_irq_rx_disable,
460 .irq_tx_complete = pl011_irq_tx_complete,
461 .irq_rx_ready = pl011_irq_rx_ready,
462 .irq_err_enable = pl011_irq_err_enable,
463 .irq_err_disable = pl011_irq_err_disable,
464 .irq_is_pending = pl011_irq_is_pending,
465 .irq_update = pl011_irq_update,
466 .irq_callback_set = pl011_irq_callback_set,
467 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
468 };
469
pl011_init(const struct device * dev)470 static int pl011_init(const struct device *dev)
471 {
472 const struct pl011_config *config = dev->config;
473 struct pl011_data *data = dev->data;
474 int ret;
475
476 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
477
478 #if defined(CONFIG_RESET)
479 if (config->reset.dev) {
480 ret = reset_line_toggle_dt(&config->reset);
481 if (ret) {
482 return ret;
483 }
484 }
485 #endif
486
487 #if defined(CONFIG_CLOCK_CONTROL)
488 if (config->clock_dev) {
489 clock_control_on(config->clock_dev, config->clock_id);
490 clock_control_get_rate(config->clock_dev, config->clock_id, &data->clk_freq);
491 }
492 #endif
493
494 /*
495 * If working in SBSA mode, we assume that UART is already configured,
496 * or does not require configuration at all (if UART is emulated by
497 * virtualization software).
498 */
499 if (!data->sbsa) {
500 #if defined(CONFIG_PINCTRL)
501 ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
502 if (ret) {
503 return ret;
504 }
505 #endif
506 /* Call vendor-specific function to power on the peripheral */
507 if (config->pwr_on_func != NULL) {
508 ret = config->pwr_on_func();
509 }
510
511 /* disable the uart */
512 pl011_disable(dev);
513 pl011_disable_fifo(dev);
514
515 /* Call vendor-specific function to enable clock for the peripheral */
516 if (config->clk_enable_func != NULL) {
517 ret = config->clk_enable_func(dev, data->clk_freq);
518 if (ret) {
519 return ret;
520 }
521 }
522
523 pl011_runtime_configure_internal(dev, &data->uart_cfg, false);
524
525 /* Setting transmit and receive interrupt FIFO level */
526 get_uart(dev)->ifls = FIELD_PREP(PL011_IFLS_TXIFLSEL_M, TXIFLSEL_1_8_FULL)
527 | FIELD_PREP(PL011_IFLS_RXIFLSEL_M, RXIFLSEL_1_2_FULL);
528
529 /* Enabling the FIFOs */
530 pl011_enable_fifo(dev);
531 }
532 /* initialize all IRQs as masked */
533 get_uart(dev)->imsc = 0U;
534 get_uart(dev)->icr = PL011_IMSC_MASK_ALL;
535
536 if (!data->sbsa) {
537 get_uart(dev)->dmacr = 0U;
538 barrier_isync_fence_full();
539 get_uart(dev)->cr &= ~PL011_CR_SIREN;
540 get_uart(dev)->cr |= PL011_CR_RXE | PL011_CR_TXE;
541 barrier_isync_fence_full();
542 }
543 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
544 config->irq_config_func(dev);
545 data->sw_call_txdrdy = true;
546 #endif
547 if (!data->sbsa) {
548 pl011_enable(dev);
549 }
550
551 return 0;
552 }
553
554 #define COMPAT_SPECIFIC_FUNC_NAME(prefix, name) _CONCAT(_CONCAT(prefix, name), _)
555
556 /*
557 * The first element of compatible is used to determine the type.
558 * When compatible defines as "ambiq,uart", "arm,pl011",
559 * this macro expands to pwr_on_ambiq_uart_[n].
560 */
561 #define COMPAT_SPECIFIC_PWR_ON_FUNC(n) \
562 _CONCAT(COMPAT_SPECIFIC_FUNC_NAME(pwr_on_, DT_INST_STRING_TOKEN_BY_IDX(n, compatible, 0)), \
563 n)
564
565 /*
566 * The first element of compatible is used to determine the type.
567 * When compatible defines as "ambiq,uart", "arm,pl011",
568 * this macro expands to clk_enable_ambiq_uart_[n].
569 */
570 #define COMPAT_SPECIFIC_CLK_ENABLE_FUNC(n) \
571 _CONCAT(COMPAT_SPECIFIC_FUNC_NAME(clk_enable_, \
572 DT_INST_STRING_TOKEN_BY_IDX(n, compatible, 0)), n)
573
574 /*
575 * The first element of compatible is used to determine the type.
576 * When compatible defines as "ambiq,uart", "arm,pl011",
577 * this macro expands to AMBIQ_UART_DEFINE(n).
578 */
579 #define COMPAT_SPECIFIC_DEFINE(n) \
580 _CONCAT(DT_INST_STRING_UPPER_TOKEN_BY_IDX(n, compatible, 0), _DEFINE)(n)
581
582 #define COMPAT_SPECIFIC_CLOCK_CTLR_SUBSYS_CELL(n) \
583 _CONCAT(DT_INST_STRING_UPPER_TOKEN_BY_IDX(n, compatible, 0), _CLOCK_CTLR_SUBSYS_CELL)
584
585 #if defined(CONFIG_PINCTRL)
586 #define PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n);
587 #define PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
588 #else
589 #define PINCTRL_DEFINE(n)
590 #define PINCTRL_INIT(n)
591 #endif /* CONFIG_PINCTRL */
592
593 #if defined(CONFIG_RESET)
594 #define RESET_INIT(n) \
595 IF_ENABLED(DT_INST_NODE_HAS_PROP(0, resets), (.reset = RESET_DT_SPEC_INST_GET(n),))
596 #else
597 #define RESET_INIT(n)
598 #endif
599
600 #define CLOCK_INIT(n) \
601 COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), (), \
602 (.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
603 .clock_id = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, \
604 COMPAT_SPECIFIC_CLOCK_CTLR_SUBSYS_CELL(n)),))
605
606 #define ARM_PL011_DEFINE(n) \
607 static inline int pwr_on_arm_pl011_##n(void) \
608 { \
609 return 0; \
610 } \
611 static inline int clk_enable_arm_pl011_##n(const struct device *dev, uint32_t clk) \
612 { \
613 return 0; \
614 }
615
616 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
pl011_isr(const struct device * dev)617 void pl011_isr(const struct device *dev)
618 {
619 struct pl011_data *data = dev->data;
620
621 /* Verify if the callback has been registered */
622 if (data->irq_cb) {
623 data->irq_cb(dev, data->irq_cb_data);
624 }
625 }
626 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
627
628 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
629 #define PL011_IRQ_CONFIG_FUNC_BODY(n, prop, i) \
630 { \
631 IRQ_CONNECT(DT_IRQ_BY_IDX(n, i, irq), \
632 DT_IRQ_BY_IDX(n, i, priority), \
633 pl011_isr, \
634 DEVICE_DT_GET(n), \
635 0); \
636 irq_enable(DT_IRQ_BY_IDX(n, i, irq)); \
637 }
638
639 #define PL011_CONFIG_PORT(n) \
640 static void pl011_irq_config_func_##n(const struct device *dev) \
641 { \
642 DT_INST_FOREACH_PROP_ELEM(n, interrupt_names, \
643 PL011_IRQ_CONFIG_FUNC_BODY) \
644 }; \
645 \
646 static struct pl011_config pl011_cfg_port_##n = { \
647 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
648 CLOCK_INIT(n) \
649 PINCTRL_INIT(n) \
650 .irq_config_func = pl011_irq_config_func_##n, \
651 .clk_enable_func = COMPAT_SPECIFIC_CLK_ENABLE_FUNC(n), \
652 .pwr_on_func = COMPAT_SPECIFIC_PWR_ON_FUNC(n), \
653 };
654 #else
655 #define PL011_CONFIG_PORT(n) \
656 static struct pl011_config pl011_cfg_port_##n = { \
657 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
658 CLOCK_INIT(n) \
659 PINCTRL_INIT(n) \
660 };
661 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
662
663 #define PL011_INIT(n) \
664 PINCTRL_DEFINE(n) \
665 COMPAT_SPECIFIC_DEFINE(n) \
666 PL011_CONFIG_PORT(n) \
667 \
668 static struct pl011_data pl011_data_port_##n = { \
669 .uart_cfg = \
670 { \
671 .baudrate = DT_INST_PROP(n, current_speed), \
672 .parity = UART_CFG_PARITY_NONE, \
673 .stop_bits = UART_CFG_STOP_BITS_1, \
674 .data_bits = UART_CFG_DATA_BITS_8, \
675 .flow_ctrl = DT_INST_PROP(n, hw_flow_control) \
676 ? UART_CFG_FLOW_CTRL_RTS_CTS \
677 : UART_CFG_FLOW_CTRL_NONE, \
678 }, \
679 .clk_freq = \
680 COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), \
681 (DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency)), (0)), \
682 }; \
683 \
684 DEVICE_DT_INST_DEFINE(n, pl011_init, PM_INST_GET(n), &pl011_data_port_##n, \
685 &pl011_cfg_port_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
686 &pl011_driver_api);
687
688 DT_INST_FOREACH_STATUS_OKAY(PL011_INIT)
689
690 #ifdef CONFIG_UART_PL011_SBSA
691
692 #undef DT_DRV_COMPAT
693 #define DT_DRV_COMPAT SBSA_COMPAT
694
695 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
696 #define PL011_SBSA_CONFIG_PORT(n) \
697 static void pl011_irq_config_func_sbsa_##n(const struct device *dev) \
698 { \
699 DT_INST_FOREACH_PROP_ELEM(n, interrupt_names, \
700 PL011_IRQ_CONFIG_FUNC_BODY) \
701 }; \
702 \
703 static struct pl011_config pl011_cfg_sbsa_##n = { \
704 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
705 .irq_config_func = pl011_irq_config_func_sbsa_##n, \
706 };
707 #else
708 #define PL011_SBSA_CONFIG_PORT(n) \
709 static struct pl011_config pl011_cfg_sbsa_##n = { \
710 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
711 };
712 #endif
713
714 #define PL011_SBSA_INIT(n) \
715 PL011_SBSA_CONFIG_PORT(n) \
716 \
717 static struct pl011_data pl011_data_sbsa_##n = { \
718 .sbsa = true, \
719 }; \
720 \
721 DEVICE_DT_INST_DEFINE(n, pl011_init, \
722 NULL, \
723 &pl011_data_sbsa_##n, \
724 &pl011_cfg_sbsa_##n, \
725 PRE_KERNEL_1, \
726 CONFIG_SERIAL_INIT_PRIORITY, \
727 &pl011_driver_api);
728
729 DT_INST_FOREACH_STATUS_OKAY(PL011_SBSA_INIT)
730
731 #endif /* CONFIG_UART_PL011_SBSA */
732
