1 /*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_lpc_sdif
8
9 #include <zephyr/drivers/sdhc.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/clock_control.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/irq.h>
15 #include <zephyr/kernel.h>
16 #include <fsl_sdif.h>
17
18 LOG_MODULE_REGISTER(sdif, CONFIG_SDHC_LOG_LEVEL);
19
20 enum mcux_sdif_callback_status {
21 TRANSFER_CMD_COMPLETE = BIT(0),
22 TRANSFER_CMD_FAILED = BIT(1),
23 TRANSFER_DATA_COMPLETE = BIT(2),
24 TRANSFER_DATA_FAILED = BIT(3),
25 };
26
27 #define TRANSFER_CMD_FLAGS (TRANSFER_CMD_COMPLETE | TRANSFER_CMD_FAILED)
28 #define TRANSFER_DATA_FLAGS (TRANSFER_DATA_COMPLETE | TRANSFER_DATA_FAILED)
29
30 #define MCUX_SDIF_RESET_TIMEOUT_VALUE (1000000U)
31
32 #define MCUX_SDIF_DEFAULT_TIMEOUT (5000U)
33
34 #define MCUX_SDIF_F_MAX MHZ(50)
35 #define MCUX_SDIF_F_MIN KHZ(400)
36
37 struct mcux_sdif_config {
38 SDIF_Type *base;
39 const struct pinctrl_dev_config *pincfg;
40 uint32_t response_timeout;
41 uint32_t cd_debounce_clocks;
42 uint32_t data_timeout;
43 const struct device *clock_dev;
44 clock_control_subsys_t clock_subsys;
45 void (*irq_config_func)(const struct device *dev);
46 };
47
48 struct mcux_sdif_data {
49 volatile uint32_t transfer_status;
50 sdif_handle_t transfer_handle;
51 struct k_sem transfer_sem;
52 struct k_mutex access_mutex;
53 #ifdef CONFIG_MCUX_SDIF_DMA_SUPPORT
54 uint32_t *sdif_dma_descriptor;
55 #endif /* CONFIG_MCUX_SDIF_DMA_SUPPORT */
56 };
57
58
mcux_sdif_transfer_complete(SDIF_Type * base,void * handle,status_t status,void * user_data)59 static void mcux_sdif_transfer_complete(SDIF_Type *base, void *handle,
60 status_t status, void *user_data)
61 {
62 const struct device *dev = (const struct device *)user_data;
63 struct mcux_sdif_data *data = dev->data;
64
65 if (status == kStatus_SDIF_DataTransferFail) {
66 data->transfer_status |= TRANSFER_DATA_FAILED;
67 } else if (status == kStatus_SDIF_DataTransferSuccess) {
68 data->transfer_status |= TRANSFER_DATA_COMPLETE;
69 } else if (status == kStatus_SDIF_SendCmdFail) {
70 data->transfer_status |= TRANSFER_CMD_FAILED;
71 } else if (status == kStatus_SDIF_SendCmdSuccess) {
72 data->transfer_status |= TRANSFER_CMD_COMPLETE;
73 } else {
74 __ASSERT(false, "Unknown status code from SD interrupt");
75 }
76 k_sem_give(&data->transfer_sem);
77 }
78
79
80 /* SDIF IRQ handler not exposed in SDK header, so declare it here */
81 extern void SDIO_DriverIRQHandler(void);
82
83 /*
84 * MCUX SDIF interrupt service routine
85 */
mcux_sdif_isr(const struct device * dev)86 static int mcux_sdif_isr(const struct device *dev)
87 {
88 SDIO_DriverIRQHandler();
89 return 0;
90 }
91
mcux_sdif_reset(const struct device * dev)92 static int mcux_sdif_reset(const struct device *dev)
93 {
94 const struct mcux_sdif_config *config = dev->config;
95 struct mcux_sdif_data *data = dev->data;
96
97 k_mutex_lock(&data->access_mutex, K_FOREVER);
98 /* Disable all interrupts */
99 SDIF_DisableInterrupt(config->base, kSDIF_AllInterruptStatus);
100
101 /* Release all bus lines */
102 (void)SDIF_Reset(config->base, kSDIF_ResetAll, MCUX_SDIF_RESET_TIMEOUT_VALUE);
103
104 /* clear all interrupt/DMA status */
105 SDIF_ClearInterruptStatus(config->base, kSDIF_AllInterruptStatus);
106 SDIF_ClearInternalDMAStatus(config->base, kSDIF_DMAAllStatus);
107 k_mutex_unlock(&data->access_mutex);
108 return 0;
109 }
110
mcux_sdif_get_host_props(const struct device * dev,struct sdhc_host_props * props)111 static int mcux_sdif_get_host_props(const struct device *dev,
112 struct sdhc_host_props *props)
113 {
114 memset(props, 0, sizeof(*props));
115 props->f_max = MCUX_SDIF_F_MAX;
116 props->f_min = MCUX_SDIF_F_MIN;
117 props->power_delay = 500;
118 props->host_caps.high_spd_support = true;
119 props->host_caps.suspend_res_support = true;
120 props->host_caps.vol_330_support = true;
121 props->host_caps.bus_8_bit_support = true;
122 props->max_current_330 = 1024;
123 return 0;
124 }
125
mcux_sdif_set_io(const struct device * dev,struct sdhc_io * ios)126 static int mcux_sdif_set_io(const struct device *dev, struct sdhc_io *ios)
127 {
128 const struct mcux_sdif_config *config = dev->config;
129 uint32_t src_clk_hz, bus_clk_hz;
130
131 if (clock_control_get_rate(config->clock_dev,
132 config->clock_subsys,
133 &src_clk_hz)) {
134 return -EINVAL;
135 }
136
137 /* If clock is set to zero, we should gate clock */
138 if (ios->clock != 0 &&
139 (ios->clock <= MCUX_SDIF_F_MAX) &&
140 (ios->clock >= MCUX_SDIF_F_MIN)) {
141 bus_clk_hz = SDIF_SetCardClock(config->base, src_clk_hz, ios->clock);
142 if (bus_clk_hz == 0) {
143 return -ENOTSUP;
144 }
145 LOG_DBG("SDIF clock set to %d", bus_clk_hz);
146 } else if (ios->clock != 0) {
147 /* Invalid clock setting */
148 return -ENOTSUP;
149 }
150
151 if (ios->bus_mode != SDHC_BUSMODE_PUSHPULL) {
152 return -ENOTSUP;
153 }
154
155 SDIF_EnableCardPower(config->base, ios->power_mode == SDHC_POWER_ON);
156
157 switch (ios->bus_width) {
158 case SDHC_BUS_WIDTH1BIT:
159 SDIF_SetCardBusWidth(config->base, kSDIF_Bus1BitWidth);
160 break;
161 case SDHC_BUS_WIDTH4BIT:
162 SDIF_SetCardBusWidth(config->base, kSDIF_Bus4BitWidth);
163 break;
164 case SDHC_BUS_WIDTH8BIT:
165 SDIF_SetCardBusWidth(config->base, kSDIF_Bus8BitWidth);
166 break;
167 default:
168 return -ENOTSUP;
169 }
170
171 if (ios->signal_voltage != SD_VOL_3_3_V) {
172 return -ENOTSUP;
173 }
174 return 0;
175 }
176
177 /*
178 * Early system init for SDHC
179 */
mcux_sdif_init(const struct device * dev)180 static int mcux_sdif_init(const struct device *dev)
181 {
182 const struct mcux_sdif_config *config = dev->config;
183 struct mcux_sdif_data *data = dev->data;
184 sdif_transfer_callback_t sdif_cb = {
185 .TransferComplete = mcux_sdif_transfer_complete,
186 };
187 int ret;
188 sdif_config_t host_config = {0};
189
190 ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
191 if (ret) {
192 return ret;
193 }
194
195 host_config.responseTimeout = config->response_timeout;
196 host_config.cardDetDebounce_Clock = config->cd_debounce_clocks;
197 host_config.dataTimeout = config->data_timeout;
198 SDIF_Init(config->base, &host_config);
199
200 SDIF_TransferCreateHandle(config->base, &data->transfer_handle,
201 &sdif_cb, (void *)dev);
202 config->irq_config_func(dev);
203
204 k_mutex_init(&data->access_mutex);
205 k_sem_init(&data->transfer_sem, 0, 1);
206 return 0;
207 }
208
mcux_sdif_get_card_present(const struct device * dev)209 static int mcux_sdif_get_card_present(const struct device *dev)
210 {
211 const struct mcux_sdif_config *config = dev->config;
212
213 return SDIF_DetectCardInsert(config->base, false);
214 }
215
216
mcux_sdif_transfer(const struct device * dev,struct sdhc_command * cmd,struct sdhc_data * data)217 static int mcux_sdif_transfer(const struct device *dev,
218 struct sdhc_command *cmd,
219 struct sdhc_data *data)
220 {
221 const struct mcux_sdif_config *config = dev->config;
222 struct mcux_sdif_data *dev_data = dev->data;
223 status_t error;
224 sdif_transfer_t transfer = {0};
225 sdif_command_t sdif_cmd = {0};
226 sdif_data_t sdif_data;
227
228 #ifdef CONFIG_MCUX_SDIF_DMA_SUPPORT
229 sdif_dma_config_t dma_config = {
230 .enableFixBurstLen = false,
231 .mode = kSDIF_DualDMAMode,
232 .dmaDesBufferStartAddr = dev_data->sdif_dma_descriptor,
233 .dmaDesBufferLen = (CONFIG_MCUX_SDIF_DMA_BUFFER_SIZE / 4),
234 .dmaDesSkipLen = 0
235 };
236 #endif /* CONFIG_MCUX_SDIF_DMA_SUPPORT */
237
238 if (cmd->opcode == SD_GO_IDLE_STATE) {
239 /*
240 * Special handling for CMD0- we want to initialize the card
241 * with 80 clocks, so we will use the SDIF_SendCardActive api
242 * to ensure that CMD0 is sent while the SEND_INITIALIZATION
243 * bit is set in the CMD register.
244 */
245 if (!SDIF_SendCardActive(config->base, MCUX_SDIF_DEFAULT_TIMEOUT)) {
246 LOG_ERR("Card clock init failed");
247 return -EIO;
248 }
249 return 0;
250 }
251
252 /* Copy Zephyr data fields to SDIF struct */
253 sdif_cmd.index = cmd->opcode;
254 sdif_cmd.argument = cmd->arg;
255 /* Lower 4 bits hold native SD response type */
256 sdif_cmd.responseType = (cmd->response_type & SDHC_NATIVE_RESPONSE_MASK);
257 transfer.command = &sdif_cmd;
258
259 if (data) {
260 transfer.data = &sdif_data;
261 memset(&sdif_data, 0, sizeof(sdif_data));
262 sdif_data.blockSize = data->block_size;
263 sdif_data.blockCount = data->blocks;
264 /*
265 * Determine command type. Note that the driver is expected
266 * to handle CMD12 and CMD23 for multiblock I/O.
267 */
268 switch (cmd->opcode) {
269 case SD_WRITE_SINGLE_BLOCK:
270 case SD_WRITE_MULTIPLE_BLOCK:
271 sdif_data.enableAutoCommand12 = true;
272 sdif_data.txData = data->data;
273 break;
274 case SD_READ_SINGLE_BLOCK:
275 case SD_READ_MULTIPLE_BLOCK:
276 sdif_data.enableAutoCommand12 = true;
277 sdif_data.rxData = data->data;
278 break;
279 case SD_APP_SEND_SCR:
280 case SD_SWITCH:
281 case SD_APP_SEND_NUM_WRITTEN_BLK:
282 sdif_data.rxData = data->data;
283 break;
284 default:
285 return -ENOTSUP;
286 }
287 }
288 dev_data->transfer_status = 0U;
289 k_sem_reset(&dev_data->transfer_sem);
290 do {
291 #ifdef CONFIG_MCUX_SDIF_DMA_SUPPORT
292 error = SDIF_TransferNonBlocking(config->base,
293 &dev_data->transfer_handle, &dma_config, &transfer);
294 #else
295 error = SDIF_TransferNonBlocking(config->base,
296 &dev_data->transfer_handle, NULL, &transfer);
297 #endif /* CONFIG_MCUX_SDIF_DMA_SUPPORT */
298 } while (error == kStatus_SDIF_SyncCmdTimeout && cmd->timeout_ms--);
299
300 if (error != kStatus_Success) {
301 return -EIO;
302 }
303 /* Wait for the command to complete */
304 while ((dev_data->transfer_status & TRANSFER_CMD_FLAGS) == 0U) {
305 if (k_sem_take(&dev_data->transfer_sem, K_MSEC(cmd->timeout_ms))) {
306 return -ETIMEDOUT;
307 }
308 }
309 if (dev_data->transfer_status & TRANSFER_CMD_FAILED) {
310 return -EIO;
311 }
312 /* If data was sent, wait for that to complete */
313 if (data) {
314 while ((dev_data->transfer_status & TRANSFER_DATA_FLAGS) == 0) {
315 if (k_sem_take(&dev_data->transfer_sem, K_MSEC(data->timeout_ms))) {
316 return -ETIMEDOUT;
317 }
318 }
319 if (dev_data->transfer_status & TRANSFER_DATA_FAILED) {
320 return -EIO;
321 }
322 }
323 /* Record command response */
324 memcpy(cmd->response, sdif_cmd.response, sizeof(cmd->response));
325 if (data) {
326 /* Record bytes transferred */
327 data->bytes_xfered = dev_data->transfer_handle.transferredWords;
328 }
329
330 return 0;
331 }
332
mcux_sdif_card_busy(const struct device * dev)333 static int mcux_sdif_card_busy(const struct device *dev)
334 {
335 const struct mcux_sdif_config *config = dev->config;
336
337 return (SDIF_GetControllerStatus(config->base) & SDIF_STATUS_DATA_BUSY_MASK) ?
338 1 : 0;
339 }
340
341 /* Stops transmission of data using CMD12, after failed command */
mcux_sdif_stop_transmission(const struct device * dev)342 static void mcux_sdif_stop_transmission(const struct device *dev)
343 {
344 const struct mcux_sdif_config *config = dev->config;
345 struct mcux_sdif_data *data = dev->data;
346
347 sdif_command_t cmd = {0};
348 sdif_transfer_t transfer = {
349 .command = &cmd,
350 .data = NULL,
351 };
352
353 cmd.index = SD_STOP_TRANSMISSION;
354 cmd.argument = 0;
355 cmd.type = kCARD_CommandTypeAbort;
356 cmd.responseType = SD_RSP_TYPE_R1b;
357
358 /* Disable transmit interrupt, since we are using blocking transfer */
359 SDIF_DisableInterrupt(config->base, kSDIF_AllInterruptStatus);
360 SDIF_ClearInterruptStatus(config->base, kSDIF_AllInterruptStatus);
361
362 LOG_WRN("Transfer failed, sending CMD12");
363 SDIF_TransferNonBlocking(config->base, &data->transfer_handle, NULL,
364 &transfer);
365 }
366
mcux_sdif_request(const struct device * dev,struct sdhc_command * cmd,struct sdhc_data * data)367 static int mcux_sdif_request(const struct device *dev,
368 struct sdhc_command *cmd,
369 struct sdhc_data *data)
370 {
371 int ret;
372 int busy_timeout = MCUX_SDIF_DEFAULT_TIMEOUT;
373 struct mcux_sdif_data *dev_data = dev->data;
374
375 ret = k_mutex_lock(&dev_data->access_mutex, K_MSEC(cmd->timeout_ms));
376 if (ret) {
377 LOG_ERR("Could not access card");
378 return -EBUSY;
379 }
380 do {
381 ret = mcux_sdif_transfer(dev, cmd, data);
382 if (data && ret) {
383 /* Send CMD12 to stop transmission after error */
384 mcux_sdif_stop_transmission(dev);
385 while (busy_timeout > 0) {
386 if (!mcux_sdif_card_busy(dev)) {
387 break;
388 }
389 /* Wait 125us before polling again */
390 k_busy_wait(125);
391 busy_timeout -= 125;
392 }
393 if (busy_timeout <= 0) {
394 LOG_DBG("Card did not idle after CMD12");
395 k_mutex_unlock(&dev_data->access_mutex);
396 return -ETIMEDOUT;
397 }
398 }
399 } while (ret != 0 && (cmd->retries-- > 0));
400 k_mutex_unlock(&dev_data->access_mutex);
401 return ret;
402 }
403
404 static DEVICE_API(sdhc, sdif_api) = {
405 .reset = mcux_sdif_reset,
406 .get_host_props = mcux_sdif_get_host_props,
407 .set_io = mcux_sdif_set_io,
408 .get_card_present = mcux_sdif_get_card_present,
409 .request = mcux_sdif_request,
410 .card_busy = mcux_sdif_card_busy,
411 };
412
413 #ifdef CONFIG_MCUX_SDIF_DMA_SUPPORT
414 #define MCUX_SDIF_DMA_DESCRIPTOR_DEFINE(n) \
415 static uint32_t mcux_sdif_dma_descriptor_##n \
416 [CONFIG_MCUX_SDIF_DMA_BUFFER_SIZE / 4] __aligned(4);
417 #define MCUX_SDIF_DMA_DESCRIPTOR_INIT(n) \
418 .sdif_dma_descriptor = mcux_sdif_dma_descriptor_##n,
419 #else
420 #define MCUX_SDIF_DMA_DESCRIPTOR_DEFINE(n)
421 #define MCUX_SDIF_DMA_DESCRIPTOR_INIT(n)
422 #endif /* CONFIG_MCUX_SDIF_DMA_SUPPORT */
423
424
425 #define MCUX_SDIF_INIT(n) \
426 static void sdif_##n##_irq_config_func(const struct device *dev) \
427 { \
428 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
429 mcux_sdif_isr, DEVICE_DT_INST_GET(n), 0); \
430 irq_enable(DT_INST_IRQN(n)); \
431 } \
432 \
433 PINCTRL_DT_INST_DEFINE(n); \
434 \
435 static const struct mcux_sdif_config sdif_##n##_config = { \
436 .base = (SDIF_Type *) DT_INST_REG_ADDR(n), \
437 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
438 .response_timeout = DT_INST_PROP(n, response_timeout), \
439 .cd_debounce_clocks = DT_INST_PROP(n, cd_debounce_clocks), \
440 .data_timeout = DT_INST_PROP(n, data_timeout), \
441 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
442 .clock_subsys = \
443 (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
444 .irq_config_func = sdif_##n##_irq_config_func, \
445 }; \
446 \
447 MCUX_SDIF_DMA_DESCRIPTOR_DEFINE(n); \
448 \
449 static struct mcux_sdif_data sdif_##n##_data = { \
450 MCUX_SDIF_DMA_DESCRIPTOR_INIT(n) \
451 }; \
452 \
453 DEVICE_DT_INST_DEFINE(n, \
454 &mcux_sdif_init, \
455 NULL, \
456 &sdif_##n##_data, \
457 &sdif_##n##_config, \
458 POST_KERNEL, \
459 CONFIG_SDHC_INIT_PRIORITY, \
460 &sdif_api);
461
462 DT_INST_FOREACH_STATUS_OKAY(MCUX_SDIF_INIT)
463
