1 /*
2 * Copyright (c) 2022 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/pm/device.h>
9 #include <zephyr/pm/device_runtime.h>
10 #include <adsp_shim.h>
11 #include <adsp_power.h>
12
13 #if CONFIG_SOC_INTEL_ACE15_MTPM
14 #include <adsp_power.h>
15 #endif /* CONFIG_SOC_INTEL_ACE15_MTPM */
16
17 #include <zephyr/logging/log.h>
18 LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF);
19
20 struct pg_bits {
21 uint32_t SPA_bit;
22 uint32_t CPA_bit;
23 };
24
25 #ifdef CONFIG_PM_DEVICE
pd_intel_adsp_set_power_enable(struct pg_bits * bits,bool power_enable)26 static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enable)
27 {
28 uint16_t SPA_bit_mask = BIT(bits->SPA_bit);
29
30 if (power_enable) {
31 sys_write16(sys_read16((mem_addr_t)ACE_PWRCTL) | SPA_bit_mask,
32 (mem_addr_t)ACE_PWRCTL);
33
34 if (!WAIT_FOR(sys_read16((mem_addr_t)ACE_PWRSTS) & BIT(bits->CPA_bit),
35 10000, k_busy_wait(1))) {
36 return -EIO;
37 }
38 } else {
39 #if CONFIG_SOC_INTEL_ACE15_MTPM
40 extern uint32_t adsp_pending_buffer;
41
42 if (bits->SPA_bit == INTEL_ADSP_HST_DOMAIN_BIT) {
43 volatile uint32_t *key_read_ptr = &adsp_pending_buffer;
44 uint32_t key_value = *key_read_ptr;
45
46 if (key_value != INTEL_ADSP_ACE15_MAGIC_KEY) {
47 return -EINVAL;
48 }
49 }
50 #endif
51 sys_write16(sys_read16((mem_addr_t)ACE_PWRCTL) & ~(SPA_bit_mask),
52 (mem_addr_t)ACE_PWRCTL);
53 }
54
55 return 0;
56 }
57
pd_intel_adsp_pm_action(const struct device * dev,enum pm_device_action action)58 static int pd_intel_adsp_pm_action(const struct device *dev, enum pm_device_action action)
59 {
60 struct pg_bits *reg_bits = (struct pg_bits *)dev->data;
61 int ret = 0;
62
63 switch (action) {
64 case PM_DEVICE_ACTION_RESUME:
65 ret = pd_intel_adsp_set_power_enable(reg_bits, true);
66
67 if (ret == 0) {
68 pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_ON, NULL);
69 }
70
71 break;
72 case PM_DEVICE_ACTION_SUSPEND:
73 pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_OFF, NULL);
74 ret = pd_intel_adsp_set_power_enable(reg_bits, false);
75 break;
76 case PM_DEVICE_ACTION_TURN_ON:
77 break;
78 case PM_DEVICE_ACTION_TURN_OFF:
79 break;
80 default:
81 return -ENOTSUP;
82 }
83
84 return ret;
85 }
86 #endif /* CONFIG_PM_DEVICE */
87
pd_intel_adsp_init(const struct device * dev)88 static int pd_intel_adsp_init(const struct device *dev)
89 {
90 pm_device_init_suspended(dev);
91 return pm_device_runtime_enable(dev);
92 }
93
94 #define DT_DRV_COMPAT intel_adsp_power_domain
95
96 #define POWER_DOMAIN_DEVICE(id) \
97 static struct pg_bits pd_pg_reg##id = { \
98 .SPA_bit = DT_INST_PROP(id, bit_position), \
99 .CPA_bit = DT_INST_PROP(id, bit_position), \
100 }; \
101 PM_DEVICE_DT_INST_DEFINE(id, pd_intel_adsp_pm_action); \
102 DEVICE_DT_INST_DEFINE(id, pd_intel_adsp_init, PM_DEVICE_DT_INST_GET(id), \
103 &pd_pg_reg##id, NULL, POST_KERNEL, \
104 CONFIG_POWER_DOMAIN_INTEL_ADSP_INIT_PRIORITY, NULL);
105
106 DT_INST_FOREACH_STATUS_OKAY(POWER_DOMAIN_DEVICE)
107
