1 /*
2 * Copyright 2018,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_mu
8
9 #include <errno.h>
10 #include <string.h>
11 #include <zephyr/device.h>
12 #include <soc.h>
13 #include <zephyr/drivers/ipm.h>
14 #include <zephyr/irq.h>
15 #include <zephyr/sys/barrier.h>
16
17 #ifdef CONFIG_HAS_MCUX
18 /* MCUX HAL uses a different header file than the i.MX HAL for this IP block */
19 #include "fsl_mu.h"
20 #else
21 #include <mu_imx.h>
22 #endif
23
24 #define MU(config) ((MU_Type *)config->base)
25
26 #if ((CONFIG_IPM_IMX_MAX_DATA_SIZE % 4) != 0)
27 #error CONFIG_IPM_IMX_MAX_DATA_SIZE is invalid
28 #endif
29
30 #define IMX_IPM_DATA_REGS (CONFIG_IPM_IMX_MAX_DATA_SIZE / 4)
31
32 struct imx_mu_config {
33 MU_Type *base;
34 void (*irq_config_func)(const struct device *dev);
35 };
36
37 struct imx_mu_data {
38 ipm_callback_t callback;
39 void *user_data;
40 };
41
42 #if defined(CONFIG_HAS_MCUX)
43 /*!
44 * @brief Check RX full status.
45 *
46 * This function checks the specific receive register full status.
47 *
48 * @param base Register base address for the module.
49 * @param index RX register index to check.
50 * @retval true RX register is full.
51 * @retval false RX register is not full.
52 */
MU_IsRxFull(MU_Type * base,uint32_t index)53 static inline bool MU_IsRxFull(MU_Type *base, uint32_t index)
54 {
55 switch (index) {
56 case 0:
57 return (bool)(MU_GetStatusFlags(base) & kMU_Rx0FullFlag);
58 case 1:
59 return (bool)(MU_GetStatusFlags(base) & kMU_Rx1FullFlag);
60 case 2:
61 return (bool)(MU_GetStatusFlags(base) & kMU_Rx2FullFlag);
62 case 3:
63 return (bool)(MU_GetStatusFlags(base) & kMU_Rx3FullFlag);
64 default:
65 /* This shouldn't happen */
66 assert(false);
67 return false;
68 }
69 }
70
71 /*!
72 * @brief Check TX empty status.
73 *
74 * This function checks the specific transmit register empty status.
75 *
76 * @param base Register base address for the module.
77 * @param index TX register index to check.
78 * @retval true TX register is empty.
79 * @retval false TX register is not empty.
80 */
MU_IsTxEmpty(MU_Type * base,uint32_t index)81 static inline bool MU_IsTxEmpty(MU_Type *base, uint32_t index)
82 {
83 switch (index) {
84 case 0:
85 return (bool)(MU_GetStatusFlags(base) & kMU_Tx0EmptyFlag);
86 case 1:
87 return (bool)(MU_GetStatusFlags(base) & kMU_Tx1EmptyFlag);
88 case 2:
89 return (bool)(MU_GetStatusFlags(base) & kMU_Tx2EmptyFlag);
90 case 3:
91 return (bool)(MU_GetStatusFlags(base) & kMU_Tx3EmptyFlag);
92 default:
93 /* This shouldn't happen */
94 assert(false);
95 return false;
96 }
97 }
98 #endif
99
imx_mu_isr(const struct device * dev)100 static void imx_mu_isr(const struct device *dev)
101 {
102 const struct imx_mu_config *config = dev->config;
103 MU_Type *base = MU(config);
104 struct imx_mu_data *data = dev->data;
105 uint32_t data32[IMX_IPM_DATA_REGS];
106 uint32_t status_reg;
107 int32_t id;
108 int32_t i;
109 bool all_registers_full;
110
111 status_reg = base->SR >>= MU_SR_RFn_SHIFT;
112
113 for (id = CONFIG_IPM_IMX_MAX_ID_VAL; id >= 0; id--) {
114 if (status_reg & 0x1U) {
115 /*
116 * Check if all receive registers are full. If not,
117 * it is violation of the protocol (status register
118 * are set earlier than all receive registers).
119 * Do not read any of the registers in such situation.
120 */
121 all_registers_full = true;
122 for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
123 if (!MU_IsRxFull(base,
124 (id * IMX_IPM_DATA_REGS) + i)) {
125 all_registers_full = false;
126 break;
127 }
128 }
129 if (all_registers_full) {
130 for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
131 #if defined(CONFIG_HAS_MCUX)
132 data32[i] = MU_ReceiveMsg(base,
133 (id * IMX_IPM_DATA_REGS) + i);
134 #else
135 MU_ReceiveMsg(base,
136 (id * IMX_IPM_DATA_REGS) + i,
137 &data32[i]);
138 #endif
139 }
140
141 if (data->callback) {
142 data->callback(dev, data->user_data,
143 (uint32_t)id,
144 &data32[0]);
145 }
146 }
147 }
148 status_reg >>= IMX_IPM_DATA_REGS;
149 }
150
151 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F
152 * Store immediate overlapping exception return operation
153 * might vector to incorrect interrupt. For Cortex-M7, if
154 * core speed much faster than peripheral register write
155 * speed, the peripheral interrupt flags may be still set
156 * after exiting ISR, this results to the same error similar
157 * with errata 838869.
158 */
159 #if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
160 barrier_dsync_fence_full();
161 #endif
162 }
163
imx_mu_ipm_send(const struct device * dev,int wait,uint32_t id,const void * data,int size)164 static int imx_mu_ipm_send(const struct device *dev, int wait, uint32_t id,
165 const void *data, int size)
166 {
167 const struct imx_mu_config *config = dev->config;
168 MU_Type *base = MU(config);
169 uint32_t data32[IMX_IPM_DATA_REGS] = {0};
170 #if !defined(CONFIG_HAS_MCUX)
171 mu_status_t status;
172 #endif
173 int i;
174
175 if (id > CONFIG_IPM_IMX_MAX_ID_VAL) {
176 return -EINVAL;
177 }
178
179 if ((size < 0) || (size > CONFIG_IPM_IMX_MAX_DATA_SIZE)) {
180 return -EMSGSIZE;
181 }
182
183 /* Actual message is passing using 32 bits registers */
184 memcpy(data32, data, size);
185
186 #if defined(CONFIG_HAS_MCUX)
187 if (wait) {
188 for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
189 MU_SendMsgNonBlocking(base, id * IMX_IPM_DATA_REGS + i,
190 data32[i]);
191 }
192 while (!MU_IsTxEmpty(base,
193 (id * IMX_IPM_DATA_REGS) + IMX_IPM_DATA_REGS - 1)) {
194 }
195 } else {
196 for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
197 if (MU_IsTxEmpty(base, id * IMX_IPM_DATA_REGS + i)) {
198 MU_SendMsg(base, id * IMX_IPM_DATA_REGS + i,
199 data32[i]);
200 } else {
201 return -EBUSY;
202 }
203 }
204 }
205
206 #else
207 for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
208 status = MU_TrySendMsg(base, id * IMX_IPM_DATA_REGS + i,
209 data32[i]);
210 if (status == kStatus_MU_TxNotEmpty) {
211 return -EBUSY;
212 }
213 }
214
215 if (wait) {
216 while (!MU_IsTxEmpty(base,
217 (id * IMX_IPM_DATA_REGS) + IMX_IPM_DATA_REGS - 1)) {
218 }
219 }
220 #endif
221
222 return 0;
223 }
224
imx_mu_ipm_max_data_size_get(const struct device * dev)225 static int imx_mu_ipm_max_data_size_get(const struct device *dev)
226 {
227 ARG_UNUSED(dev);
228
229 return CONFIG_IPM_IMX_MAX_DATA_SIZE;
230 }
231
imx_mu_ipm_max_id_val_get(const struct device * dev)232 static uint32_t imx_mu_ipm_max_id_val_get(const struct device *dev)
233 {
234 ARG_UNUSED(dev);
235
236 return CONFIG_IPM_IMX_MAX_ID_VAL;
237 }
238
imx_mu_ipm_register_callback(const struct device * dev,ipm_callback_t cb,void * user_data)239 static void imx_mu_ipm_register_callback(const struct device *dev,
240 ipm_callback_t cb,
241 void *user_data)
242 {
243 struct imx_mu_data *driver_data = dev->data;
244
245 driver_data->callback = cb;
246 driver_data->user_data = user_data;
247 }
248
imx_mu_ipm_set_enabled(const struct device * dev,int enable)249 static int imx_mu_ipm_set_enabled(const struct device *dev, int enable)
250 {
251 const struct imx_mu_config *config = dev->config;
252 MU_Type *base = MU(config);
253 #if defined(CONFIG_HAS_MCUX)
254 #if CONFIG_IPM_IMX_MAX_DATA_SIZE_4
255 if (enable) {
256 MU_EnableInterrupts(base, kMU_Rx0FullInterruptEnable);
257 MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable);
258 MU_EnableInterrupts(base, kMU_Rx2FullInterruptEnable);
259 MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
260 } else {
261 MU_DisableInterrupts(base, kMU_Rx0FullInterruptEnable);
262 MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable);
263 MU_DisableInterrupts(base, kMU_Rx2FullInterruptEnable);
264 MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
265 }
266 #elif CONFIG_IPM_IMX_MAX_DATA_SIZE_8
267 if (enable) {
268 MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable);
269 MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
270 } else {
271 MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable);
272 MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
273 }
274 #elif CONFIG_IPM_IMX_MAX_DATA_SIZE_16
275 if (enable) {
276 MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
277 } else {
278 MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
279 }
280 #else
281 #error "CONFIG_IPM_IMX_MAX_DATA_SIZE_n is not set"
282 #endif
283 #else
284 #if CONFIG_IPM_IMX_MAX_DATA_SIZE_4
285 if (enable) {
286 MU_EnableRxFullInt(base, 0U);
287 MU_EnableRxFullInt(base, 1U);
288 MU_EnableRxFullInt(base, 2U);
289 MU_EnableRxFullInt(base, 3U);
290 } else {
291 MU_DisableRxFullInt(base, 0U);
292 MU_DisableRxFullInt(base, 1U);
293 MU_DisableRxFullInt(base, 2U);
294 MU_DisableRxFullInt(base, 3U);
295 }
296 #elif CONFIG_IPM_IMX_MAX_DATA_SIZE_8
297 if (enable) {
298 MU_EnableRxFullInt(base, 1U);
299 MU_EnableRxFullInt(base, 3U);
300 } else {
301 MU_DisableRxFullInt(base, 1U);
302 MU_DisableRxFullInt(base, 3U);
303 }
304 #elif CONFIG_IPM_IMX_MAX_DATA_SIZE_16
305 if (enable) {
306 MU_EnableRxFullInt(base, 3U);
307 } else {
308 MU_DisableRxFullInt(base, 3U);
309 }
310 #else
311 #error "CONFIG_IPM_IMX_MAX_DATA_SIZE_n is not set"
312 #endif
313 #endif
314
315 return 0;
316 }
317
imx_mu_init(const struct device * dev)318 static int imx_mu_init(const struct device *dev)
319 {
320 const struct imx_mu_config *config = dev->config;
321
322 MU_Init(MU(config));
323 config->irq_config_func(dev);
324
325 #if defined(CONFIG_IPM_IMX_FW_READY_REPLY)
326 /* Send FW_READY reply message - this is used on host side,
327 * for handshake communication.
328 *
329 * An example is in Linux, imx_dsp_rproc driver, where
330 * after starting the remote processor, the host is waiting for a
331 * FW_READY reply.
332 */
333 MU_Type * base = MU(config);
334
335 MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger |
336 kMU_GenInt1InterruptTrigger |
337 kMU_GenInt2InterruptTrigger |
338 kMU_GenInt3InterruptTrigger);
339 #endif
340
341 return 0;
342 }
343
344 static DEVICE_API(ipm, imx_mu_driver_api) = {
345 .send = imx_mu_ipm_send,
346 .register_callback = imx_mu_ipm_register_callback,
347 .max_data_size_get = imx_mu_ipm_max_data_size_get,
348 .max_id_val_get = imx_mu_ipm_max_id_val_get,
349 .set_enabled = imx_mu_ipm_set_enabled
350 };
351
352 /* Config MU */
353
354 static void imx_mu_config_func_b(const struct device *dev);
355
356 static const struct imx_mu_config imx_mu_b_config = {
357 .base = (MU_Type *)DT_INST_REG_ADDR(0),
358 .irq_config_func = imx_mu_config_func_b,
359 };
360
361 static struct imx_mu_data imx_mu_b_data;
362
363 DEVICE_DT_INST_DEFINE(0,
364 &imx_mu_init,
365 NULL,
366 &imx_mu_b_data, &imx_mu_b_config,
367 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
368 &imx_mu_driver_api);
369
imx_mu_config_func_b(const struct device * dev)370 static void imx_mu_config_func_b(const struct device *dev)
371 {
372 IRQ_CONNECT(DT_INST_IRQN(0),
373 DT_INST_IRQ(0, priority),
374 imx_mu_isr, DEVICE_DT_INST_GET(0), 0);
375
376 irq_enable(DT_INST_IRQN(0));
377 }
378
