1 /*
2  * Copyright (c) 2023 Jerzy Kasenberg.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/device.h>
8 #include <zephyr/drivers/hwinfo.h>
9 #include <soc.h>
10 
z_impl_hwinfo_get_reset_cause(uint32_t * cause)11 int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
12 {
13 	int ret = 0;
14 	uint32_t reason = CRG_TOP->RESET_STAT_REG;
15 	uint32_t flags = 0;
16 
17 	/*
18 	 * When POR is detected other bits are not valid.
19 	 */
20 	if (reason & CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk) {
21 		flags = RESET_POR;
22 	} else {
23 		if (reason & CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk) {
24 			flags |= RESET_PIN;
25 		}
26 		if (reason & CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk) {
27 			flags |= RESET_SOFTWARE;
28 		}
29 		if (reason & CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk) {
30 			flags |= RESET_WATCHDOG;
31 		}
32 		if (reason & CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk) {
33 			flags |= RESET_WATCHDOG;
34 		}
35 		if (reason & CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk) {
36 			flags |= RESET_DEBUG;
37 		}
38 	}
39 
40 	*cause = flags;
41 
42 	return ret;
43 }
44 
z_impl_hwinfo_clear_reset_cause(void)45 int z_impl_hwinfo_clear_reset_cause(void)
46 {
47 	int ret = 0;
48 
49 	CRG_TOP->RESET_STAT_REG = 0;
50 
51 	return ret;
52 }
53 
z_impl_hwinfo_get_supported_reset_cause(uint32_t * supported)54 int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
55 {
56 	*supported = (RESET_PIN
57 		| RESET_SOFTWARE
58 		| RESET_POR
59 		| RESET_WATCHDOG
60 		| RESET_DEBUG);
61 
62 	return 0;
63 }
64